How can two hardware modules described in Atlas synchronize their communication, this lecture will
explain the handshaking mechanism as a way of data exchange synchronization.
Software functions communicate through their arguments in zero time, however, hardware modules which
correspond to design top functions in Etchells communicate through ports with associated protocols,
usually taking a couple of cycles to perform the desired data exchange and a simplified model.
Hardware modules are connected.
Why are a bunch of wires or signals?
The values on these wires are valid at a specific time or during a time slot.
Therefore, two modules can properly communicate if they are ready for exchanging data and are aware
of these timings.
This concept is usually called synchronization, in addition to timing, the number of wires is also
important and two modules should also be aware of that.
Hard for module use ports to communicate together.
The number of signals and their characteristics are defined as the port interface, the associated protocol
assigned to each interface defines the mechanism of data transaction and the corresponding port.
In other words, a protocol defines the event sequences of the synchronization mechanism between two
connected ports.
The port interface and protocol concepts are very close and related.
Therefore they are usually used interchangeably.
As we know, the top function in a necklace is synthesized into a hardware module, also its arguments
and return value are map to ports in the corresponding hardware module called by value a scalar.
Arguments are assigned to input ports.
Call Bio-Reference a scalar.
Arguments are mapped to output or input ports.
Arry and Pointer arguments can provide access to memories, so they need special attention in hardware.
Although each argument is assigned to a port, the C C++ software language does not have any feature
to define the interface and protocol assigned to each port.
Therefore, the actual Astal should provide the mechanism to define interfaces and their corresponding
protocols.
The White Essentialists provides a complete list of industrial base interfaces to be assigned to design
top function arguments.
It also considers default interfaces for each argument based on the type of the design and access methods
to the arguments.
Modules on an FPGA usually uses the same clock signal.
Therefore, the synchronization between them to generate and consume valid data is not so complicated.
In simple cases, the shared clock can be used to synchronize a data transaction.
In other cases, a few signals can be used to implement a type of handshaking protocol between two modules.
However, when the hardware module inside an FPGA communicates with the peripheral, then synchronization
between two modules is crucial and needs special attention.
The communication among hardware in FPGA can be categorized into two groups, communication among modules
inside the FPGA and communication between modules inside the FPGA and the peripherals outside each of
these communications requires its own interfaces and protocols.
What is the basic idea of communication protocol between two harder modules, the next lecture will
answer this question.
These are our takeaway messages.
Two modules can properly communicate if they are ready for exchanging data and are aware of these timings.
This concept is usually called synchronization.
There are two data exchange groups among hardware modules in each of us, communication between modules
inside an FPGA and communication between the modules inside an FPGA and the peripheral outside FPGA.
Now, the quiz question give a couple of examples for data communication between a module inside an
FPGA and a peripheral outside FPGA.