How can we control the execution of a hardware module generated by this flow, this lecture will explain
how to read the status of a module or command that to start its task.
Balaklava interface protocols provide the mechanism for controlling the operation of an artificial module
such that other modules and software applications can control an RTL module using the associated block
level interface.
By default, a Balaklava level interface protocol is added to the design, the ports of the block level
interface control when the block can start processing data upon or start indicate when it is ready to
accept new inputs.
AP underscore already and indicate if the design is idle.
I underscore idle or has completed operation.
AP underscored the.
Why does List uses the following interface types to specify whether the article is implemented with
block level handshake signals?
APC, TRL, one, APC, TRL, Leches, APC, Tiaro chain and s accelerate block level handshake signals
specify the following one.
The design kind of start to perform the operation when the operation ends, when the design is idle
and ready for new inputs.
You can specify the level of your protocols and the function or the function return if the key plus
plus code does not returning value, you can easily specify the block level II protocol on the function
return if the C C++ code uses a function, return Y to create an output port API return for the return
value.
The AP city elections block level II protocol is the default, the following figure shows the resulting
article Ports and Behavior.
When White House implements TRL on a function in this example, the function returns a value using the
return statement and pointer, such as creates the AP return output port in the article design if the
function return statement is not included in the C C++ code.
This port is not created.
When they pass, the signal is high, the module is in the recent state and cannot do anything, a low
lying state on the apress, the signal enabled the module to accept the handshake commands.
Now the module is idle and ready to start performing its task whenever it receives a high logic value
on the AP starting point.
One day we started to receive the module puts the API the signal to zero value, indicating the design
is no longer idle.
The module is performing its task and can receive input data and generate output data when it finishes
its task, the AP done goes high and outputs are ready to be read by other modules or software.
The next lecture will demonstrate the global interface signaling through a multi cycle example.
These are our takeaway messages, software functions running on a processor or hardware modules inside
FPGA can control or monitor a natural gas module through block level interface NPC, TRL X is the default
block level interface.
Download the White House high level sentence's user guide, Euge thirteen ninety nine document and in
pages 219 to 212, the study, the AP underscore Citarella, underscore X and AP underscore citral,
underscore chain interfaces.