How can we show the behavior of the black level interface, ABC, TRL, X in practice, this lecture
will take an example of a simple floating point accumulator to represent the signaling of the APC TRL
as interface in action by using an integrated logic analyzer.
Let's consider the floating point accumulator circuit as an example of a multi cycle designing this
circuit receives a sequence of floating point numbers and accumulates that as its output.
For example, this figure shows the output generated for this sequence of input as shown in this diagram.
Our design is simple.
It consists of a floating point adder and the register.
Now, let's describe the floating point accumulator initialised the top function, receives an input
and generates an out, we need a static variable to save the previous results, then we need the addition.
And finally sending out the results.
As the state register provides the output directly, we should ensure that the center system does not
optimize that and merge it with other registers in the article design after synthesis.
For this purpose, we can add the volatile modifier to the static variable declaration.
Now we should add the interfaces.
First of all, let's add the module level interface here, the ABC, TRL X is selected.
We will control the hardware module execution and run that whenever an input value is ready.
Then we have the argument interfaces.
Also, we apply the pipeline optimization program.
However, because of the data dependency on the code, the function cannot be pipelined.
We will see this later in this lecture.
Note that instead of using the volatile modifier, we can guide the tool to implement the output with
a dedicated register for this purpose, we should add the keyboard register at the end of the output
interface definition.
This slide shows the final design involved.
We have the float accumulator IP, then we have another IP that receives the accumulator output and
shows that on the seven segment display.
However, as we cannot generate floating point numbers easily on the board using the basic input mechanisms
such as light switches, we need another IP to generate a sequence of floating point numbers.
This IP generates a floating point number whenever we requested that through its input by a single cycle
pulse, which a push button will generate.
Therefore, we needed the bouncer and Pulcinella authorities also, we use the AP done output of the
number generator IP to start the accumulator task.
Let's have a look at the number generator type.
It has an area of 10 numbers which sends out one of them when it's requested, the top function has
one input and output.
To keep track of the air index, we need a static variable, then we define the register to keep the
generated output stable, to be used by the downstream.
Then the code checks to generate input.
If it's one, it uses the index register to access a number in the area and send that out.
Then it increments the index and makes sure that it is between zero and nine as the defined area has
only 10 elements.
The AP interface is also assigned to the module.
Now let's see the design in action.
Let's first ride the float accumulator, invite socialists.
For this purpose, open the White House and create a new project with the name of Fallowed underscore
accumulator.
That's what researchers said the top function name to float, underscore, accumulate.
And don't forget to select the basis to report as a target FPGA platform.
Download the design and test bench files from the resources folder attached to this lecture and add
them to the created project.
Often the design they're fighting, it defines the data type macro, which here is float.
Then open the design source file and have a look at the code.
This is the code that we saw earlier in this lecture.
Open the first page header for it defines the end macro to represent the value of 10.
Now, let's look at a test source, Sourcefire, it defines a software implementation for the design
as the golden model then in the main function.
An area of 10 floating point value is declared, then it calls the design and times and prints out doubts.
After that, it checks the final result with that of the Golden Model.
Let's perform the simulation.
The result confirms the design functionality, correctness.
After finishing the simulation, successfully performed a high level synthesis.
The result shows that the design is not pipelined properly as initiation in Tarawallie is, the main
reason is the data dependency between two consecutive function calls on the ATC underscore state register.
Export RTL IP to be used later in the project.
Now let's describe the floating point display driver invited suchness create a new white essentialist
project with the name of display underscore float Dasch White Essentialists for the basis Thibaut.
Download the design files and add that to the created project.
Open the design source finds the display driver function utilizes a four state FSM to show four digits
on the seven segment displays.
They're designed to function, receives a floating point number.
Exact digits and calls the display underscore driver function to generate the corresponding sound segment
signals the design, assumes that the number has a two digit fraction of what?
Synthesize the Code and Export Authority like.
We should design another IPO to generate floating point numbers.
Create a new White House project with the name of generate underscore, fallowed, underscore, no dash
white assiduous for the base's triple.
Download the design files and add them to the project's.
Have a look at the design header and Sourcefire, we saw them earlier in this lecture, synthesize the
code and export the artillery.
Now, generically, we want a project with the name of float underscore accumulator that we want.
Create a new block design.
And five ipis to divide the repository.
The bouncer display float.
Float accumulator generates float numbers and pulse generator ipis instantiate the IPS and connect them
together.
And your IP for monitoring some of the design signals customise the IP by adding seven probes to the
IP, then connect that to the design signals.
Downloaded this on Konstantine and add that to the project, then generic, that refuge's.
Defined the trigger boolean expression and a start ilf for sampling, press the up push button on the
board and examine the signals on Dialla waveform window.
Try to understand the block level interface signals in the Ayalew waveforms.
Play with the board and check the design functionality.
The next letter, we look at airport level interface that introduces a validated signal attached to
each argument.
These are our takeaway messages, the high level synthesis process may optimize the code by merging
or removing registers and variables defined in the code.
If you want to keep a register, then use a volatile modifier when you declare the corresponding variable.
Describing hardware modules in Etchells to generate input data for a design can be helpful in several
occasions.
Now, the police question, what is the alternative way of using the volatile modifier to keep the register
attached to the accumulator designs out with port?