How can we design the counter based digital dice for the basis through what this lecture will cope with
this question?
Our digital life circuit receives a one bit input, which is connected to a push button and generates
a random number between one and six that will be shown on a seven segment display.
The counter based approach utilizes a 32 bit counter to model a spinning wheel.
The counter continuously counts between zero to two to the power of 32 minus one, then whenever we
push the button, we'll read the counter while it is still running.
Then we can find the modulus six of the number, which results in a number between zero and five.
Incrementing this number generates the final random number between one and six.
Now, let's implement our idea in this open the way to such a list and generate a new project with the
name of dice, underscore, roller, underscore, counter dash.
What is a.
Accordingly, choose unrest, caroler underscore counter as a design to function and select the basis
three as the underlying FPGA board.
Download the design and test files from the resources folder attached to this lecture and add them to
the project.
The design, Heather Fine, defines an array containing the seven segment codes, four digits from zero
to nine.
The Getaround function and the design Sourcefire implement a circular 32 bit counter that should continuously
count in each clock cycle.
It returns the Modula six plus one of its current number, when we call that the top function, has
an input argument called Rove connected to a push button and two outputs that will drive a seven segment
display on the basis three board.
The pipeline optimization is also applied on the top, one of the top function defines a static variable
that contains the last generated random number.
It calls the Getaround sub function in each Cluck's cycle.
Note that we expect that the description follows the risky design approach, which means its initiation
into a wall is one and the top function is called in each clock cycle.
The top function checks the roll input and if it is one, it selects the number generated by the function
as the final random number.
Note that the rolling input is connected to a push button on the board.
The last two lines in the top function send the corresponding seven segment code and enabled signals.
That has been Sourcefire defines a map variable to return the BCT number corresponding to each segment
code, then the main function calls are designed to function several times in Tunis looks the inner
loop uses a random number of iterations to call the top function while the roll signal is zero.
This loop model, the time when the design runs in the PJ and push button is not pressed.
The outlook calls the top function with the roll signal equal to one, in this case, the design generates
a random number.
Let's simulate the code and check it out.
Now, let's synthesize the code and make sure that the result of the design is pipelined with the initiation
interval of one.
The analysis perspective confirms this expectation.
As can be seen, the initiation interval is one clock cycle.
Whereas the design latency is thirty seven cycles.
Now let's explore the Arctic IP to be used in every one of the projects.
Creative, you want the project with the name of dice, underscore, roller, underscore, count or
dashboard and select the basis to report as a target FPGA platform.
Create a new blog design and the generated IP, along with the bouncer and pulse generator IPS into
the pivotal repository.
And I appeal to the design area and connect them together, changed a port named appropriately.
Download the consent file from the resources folder attached to this lecture and add that to the report
of the project's.
Now, generate down to product, create the ideal wrapper, and finally generate FPGA bitstream, program
the FPGA and examine the design on the board.
What is the pseudo random number generator and how can we use that to implement the digitalise the next
lecture will answer these questions.
This is our takeaway message acounter can be used to implement is spinning.
Now, the question changed the code to implement a circular counter from one to six and check the design
on the FPGA.