1 00:00:01,040 --> 00:00:04,160 What is a linear feedback shift register, Eleazar? 2 00:00:05,300 --> 00:00:08,890 And how can we use that for a pseudo random number generator? 3 00:00:10,780 --> 00:00:17,470 This lecture will address these questions, in addition, it will explain how to describe that dimensionless. 4 00:00:22,100 --> 00:00:28,880 A linear feedback shift register at FSR is a shift register whose input it is a linear function of its 5 00:00:28,880 --> 00:00:29,930 previous state. 6 00:00:31,050 --> 00:00:36,000 The most commonly used linear function of single bits is an exclusive or. 7 00:00:37,710 --> 00:00:45,060 Therefore, I FSR is usually a sheep producer whose input bit is the X or of some of its value. 8 00:00:45,090 --> 00:00:53,040 It's one of the main applications of the elephants are is generating pseudo random numbers and modulo 9 00:00:53,040 --> 00:01:00,020 two polynomial can be used to represent an Alpha SA, which is called its characteristic polynomial. 10 00:01:00,750 --> 00:01:04,050 The coefficients of this polynomial are ones or zeros. 11 00:01:04,590 --> 00:01:08,700 The one coefficients correspond to the connections to the first bit. 12 00:01:09,300 --> 00:01:18,810 For example, in this example, positions zero, one, two, three and four denoted by X zero x1 x2 13 00:01:19,080 --> 00:01:23,260 three and four respectively have connections to the first. 14 00:01:24,570 --> 00:01:29,340 This is another FSR example, along with its characteristic polynomial. 15 00:01:31,800 --> 00:01:34,350 Let's consider this three with an officer. 16 00:01:35,490 --> 00:01:40,470 The initial value of their FSR is called the sea, the sea, it cannot be zero. 17 00:01:41,850 --> 00:01:48,000 Because the operation of the register is deterministic, this stream of values produced by the register 18 00:01:48,150 --> 00:01:52,400 is completely determined by its current or previous state. 19 00:01:52,770 --> 00:01:59,490 Likewise, because the register has a finite number of possible estates, it must eventually enter a 20 00:01:59,490 --> 00:02:00,510 repeating cycle. 21 00:02:00,870 --> 00:02:08,160 However, another officer with a well chosen feedback function can produce a sequence of bits that appears 22 00:02:08,160 --> 00:02:16,000 random and has a very long cycle and end with FSR that has two to the power of and minus one. 23 00:02:16,020 --> 00:02:18,870 Different states called maximal length. 24 00:02:23,380 --> 00:02:27,130 It positions that affect the next estate are called the tax. 25 00:02:28,150 --> 00:02:33,880 In this diagram, the tops are 16, 14, 13 and 11. 26 00:02:34,920 --> 00:02:38,560 A maximum length of FSR produces an end sequence. 27 00:02:38,880 --> 00:02:46,020 The thing is, it cycles through all possible due to the power of and minus one two states except for 28 00:02:46,020 --> 00:02:48,450 the state where all bets are Zeitels. 29 00:02:52,560 --> 00:02:57,200 The following table lists maximum length polynomials for analysis. 30 00:02:59,730 --> 00:03:06,180 Now, we should describe another FACA in place for this purpose, let's consider this 32 bit maximum 31 00:03:06,180 --> 00:03:07,440 length Alcazar. 32 00:03:07,920 --> 00:03:13,230 Please pay attention to the bit indices, which is a slightly different from the area indices in C, 33 00:03:13,230 --> 00:03:21,510 C plus plus the C function describing the FSR accepts a 32 bit and a single bit inputs as the C and 34 00:03:21,510 --> 00:03:22,320 the load sigma. 35 00:03:24,960 --> 00:03:27,790 We should define a static variable as a shift register. 36 00:03:28,590 --> 00:03:31,320 Please consider the bits indices in this variable. 37 00:03:32,680 --> 00:03:39,130 If the little signal is one we initialize, the letters are with the C, this diagram shows the officer 38 00:03:39,220 --> 00:03:40,720 with the modified indices. 39 00:03:41,850 --> 00:03:44,130 Now, let's describe the feedback function. 40 00:03:47,830 --> 00:03:50,380 And finally returns that FSR value. 41 00:03:54,000 --> 00:03:58,410 Now, let's ascribe that FSR based digital dice in white Essentialists. 42 00:03:59,570 --> 00:04:06,080 First of all, open the White House and create a new project with the name of Dyce, underscore, roller, 43 00:04:06,080 --> 00:04:13,220 underscore LFR Dash White secessionists to the dice, underscore roller, underscore LFR as a design 44 00:04:13,220 --> 00:04:17,780 top function name and selected basis to report and the target FPGA class for. 45 00:04:31,750 --> 00:04:37,810 Download the design and test bench files from the resources folder attached to the selection and the 46 00:04:37,810 --> 00:04:39,820 files to the creative project. 47 00:04:48,150 --> 00:04:53,880 How we look at the design Sourcefire, the pseudo random stop function implements that officer explained 48 00:04:53,880 --> 00:04:54,900 earlier in this lecture. 49 00:04:56,620 --> 00:05:02,970 They get suspension calls that FSR and returns modulars six plus one of the random. 50 00:05:04,380 --> 00:05:09,660 If it is the first time it passes the seat with one on the loud signal to the al FSR functio. 51 00:05:11,420 --> 00:05:17,900 They're designed to function checks, the roll input, if it is one, then it calls the Getaround function, 52 00:05:18,230 --> 00:05:22,670 then returns a certain segment code corresponding to the received a random number. 53 00:05:23,610 --> 00:05:27,840 Notice that the pipeline optimization pragma is applied to the top function. 54 00:05:31,600 --> 00:05:37,230 The test bench function is very similar to the test bench function explained in the previous lecture. 55 00:05:40,710 --> 00:05:43,920 Now, let's simulate the code and synthesize that. 56 00:05:57,760 --> 00:06:04,330 The analysis perspective confirms the risky design approach as a design initiation in turmoil is what? 57 00:06:09,410 --> 00:06:14,300 Now let's explore the IP and instantiate that in a we want to project. 58 00:06:23,860 --> 00:06:30,790 Created, we want a project with the name of Dyce, underscore, roller, underscore FSR Dashboard and 59 00:06:30,790 --> 00:06:34,000 select the basis storyboard as the target FPGA class for. 60 00:06:46,250 --> 00:06:52,670 Create a new blog design and the generated IP, along with the bouncer and a pulse generator, ipis 61 00:06:52,670 --> 00:06:54,290 into the Riverdale, the repository. 62 00:06:55,260 --> 00:07:00,970 And ipis to the design area and connect them together, change the port names appropriately. 63 00:08:25,460 --> 00:08:31,730 Download the consent file from the resources folder attached to this lecture and add that to the wider 64 00:08:31,730 --> 00:08:32,300 project. 65 00:08:52,950 --> 00:08:59,880 Now, generally, down products create the ideal wrapper and finally generate the FPGA with three programmed 66 00:08:59,880 --> 00:09:02,540 FPGA and examine the design on the board. 67 00:10:00,980 --> 00:10:06,260 And this video is the last letter in the section that explains how to implement a digital device on 68 00:10:06,260 --> 00:10:12,260 the basis report, the next lecture will give you a few exercises to practice and master what you've 69 00:10:12,260 --> 00:10:13,700 learned throughout this section. 70 00:10:17,230 --> 00:10:18,870 These are our takeaway messages. 71 00:10:19,750 --> 00:10:23,450 And officers can be used to generate pseudo random numbers. 72 00:10:24,530 --> 00:10:29,990 And with maximum length and officer has to go to the power of and minus one state's. 73 00:10:33,080 --> 00:10:38,840 Now, the police question right there, telescope for analysis are with this feedback polynomial.