How can we describe the transmitter module invited, such as this lecture will answer this question.
First of all, let's have a big picture of the final design involved and IPPs involved.
We have your transmitter IP described in necklace, then a border generator provides the Boatwright's
signal, the AP data input is connected to the light switches on the board and finally and the bouncer
and a pulse generator connect the start to a push button on the board.
Let's talk about the you are transmitter.
The main task of our transmitter, IP, is sending out 10 bits of data, one by one, and receiving
a pulse on the board right signal.
Initially, the design is waiting for a pulse on a starting point to begin its task, therefore, the
design would have to sit idle and transmit.
And I illustrate the signal is waiting for a pulse on the starting and in the transmitter state, it
sends out one bit of the data.
Whenever it receives a pulse on the board right signal, the circuit stays in the transmitter state
until it sends out all the 10 bits of data a can help to determine the time the circuit should go to
the idle state.
Let's describe the circuit in each of us, first of all, we define an enumeration data type to represent
the circuit states, then we should define the top function that has three inputs and one output to
static variables should be defined in the design.
The first one keeps the circuit state and the other is used as the counter.
Two temporary variables are defined to save the intermediate values of state and top function output.
The start with date of its unstopped or concatenated to form a simple 10 with one, then we have the
state machine with two states.
After that, we should modify the state and the U.S. on this 46 variables.
If the circuit receives a single pulse on the starting point when it is in the idle state, it goes
to to transmit state, otherwise it stays in the middle seat in the transmit to state, the behavior
of the design is a little bit complex.
First, it checks the bold red signal.
If it is one, the circuit should send out one bit of the data value and increment the counter and stay
in the transmit state.
However, when the counter is ten, the state machine goes to the idle state.
If the bold red signal is zero, then the circuit sends out the last send data of it to keep the output
stable and stays in the transmit state.
The basis the report includes a USB port bridge attached to the Connector J4 that allows you to use
PC applications to communicate with the board using standard windows, comport commands to on board
a satis LEDs, provide visual feedback on the traffic flowing through the port, the transmitter, the
LDA and the receiver LDA.
This figure shows the board configuration that hosts you are transmitter design.
The starting point is connected to the push button, as I mentioned earlier, the USPI data connection
also can be used as the report on this particular.
Now, let's describe the circuit, invite Essentialists, we should describe to ipis the Boulder generator
and the transmitter.
Let's first describe the board, regenerate, create a new white essentialist project with the name
of board, underscore great underscore generator, dash white Essentialists and select the board regenerator
as a top function name and choose the basis to board as a target FPGA platform.
Download the design and test bench files from the resources folder attached to this lecture and add
them to the project.
Open the design source, why this design is very similar to the single cycle regular process design
explained in the utility section, except here the parts per year is ten thousand four hundred and sixty
to generate pulses with the frequency of ninety six hundred hertz or ninety six hundred pulses per second,
which is our selected.
You are portrayed in this project.
For the sake of simplicity.
We can assign 20 to the board rate number just for simulation.
Then we can perform the simulation to make sure the code functionality is correct.
After that, we should restore the proper value to the boards right number and synthesize the code and
generate the corresponding IP.
Now create another white, such a site with the name of your art underscore transmitter that Schweitzer
and tools that you are a transmitter as a top functionary, then select the basis three board as a target
FPGA.
Download the design and test bench fines from the resources folder attached to this lecture and add
them to the project's.
Open the design Sourcefire, it contains the top function and description explained earlier in the structure.
Have a look at the Test match for the sea main function assigns the value of zero one zero zero zero
zero zero one to the data variable as the input parallel data.
Then it calls the design top function several times to generate the board's pulses board rate signal
variable alternates between zero and one in the form.
Perform the simulation and check it out here, we can check the design functionality and not the timing.
Then perform the high level syntheses and TLC called Simulation.
In the way for future, check the outputs and make sure that the output sequence is correct here is
still we cannot check the timing as the design requires Boldrin generator IP, which is available during
Logic's sentences in the regard on project.
Export our IP to be used in environmental projects.
Now let's create a new revival project with the name of your art underscore transmitter Dash Willott
and select bassist reborn as a Target FPGA platform.
Curate a new blog design and ad for Ipis to deliver the repository, the bouncer, pulse generator,
Boldrin generator and the user transmit.
Instantiate the IPS and connect them together and change the name properly.
Download the file and add that to the device, the project.
Generate FPGA bitstream and programmable.
On your computer connected to the bases, report on a serial terminal program.
Such as Turtur.
You can download that at this address.
Go to set up serial port, then to the proper compost that is corresponding to your birth connection.
Select ninety six hundred as the speed and keep the default values for other options and press.
OK, now the terminal is ready to receive data from your board.
Subtask called up a character on the slide switches, the code is zero one zero zero zero zero zero
one.
Then press the push button.
You should see the character inside the terminal running on your computer.
Sadowsky called for other letters and numbers and checked the terminals.
To understand the design timing, let's follow the runtime debugging mechanism using IP, explain throughout
this course and dial IP to the design.
Now double click on that to customize the IP, select the native as the monitor type.
Consider three Poirot's.
Notes that as each You Are Baudry period contains ten thousand two hundred sixteen clock cycles.
Then for sending 10 minutes over art collection, we need at least ten thousand two hundred and sixteen,
multiply ten samples.
Therefore in the sample data depth option, choose one hundred thirty one thousand seventy two.
Now go to the proper tab and select one trigger and to date Uprose.
Close the window and make the connections.
First of all, connect the clock signal, then connect zero to the pulse generator.
Note that this probe is a trigger signal that triggers the sampling process.
Then connect one to the board, regenerator out and finally connect the probe, two to the transmitter
output now generated FPGA bitstream and programmed aboard.
After programming the board, you should see the isolator perspective in the regard idee.
In the three years, a window click on the plus icon and select the only trigger signal in the least,
change the value from X to one.
Now go to the setting, S.W. underscore Ilea, underscore one tab and make sure that the trigger position
window option is Zeil.
Now go to the status, stop and press on the wrong trigger for this, ERICO, now on the board, said
the character Askey code on the slide switches and pressed our push button.
Dialogue will start sampling and show the waveforms on its way, form viewer, check the timing and
value correctness.
The next lecture explains how to design the yuan's receiver module in Etchells.
These are our takeaway messages, a counter and a state machine between states can model if you are
transmitter, it can be used to monitor the you are transmitter signals are the on.
Now, the quiz question modified the code to follow our coding style, explained throughout the course.