Designing and debugging the new art receiver is the goal of this lecture.
The receiver module receives a packet of data serially.
Here we can see there are 10 bits of data containing it, start with a data bits and want to stop it.
The circuit has two states idle and receive.
Initially, the circuit is in the idle state waiting to receive this target when it receives the start
with, it goes to the receiver state to receive a database.
Are still a state accountable variable counts the number of received data.
Finally, if the module receives the stop it, it goes back to the idle, ready for the next data packet.
Let's have a look at the rest of our code initialised.
First, we define an enumeration type to describe the circuit states they design.
Top function has for arguments two inputs and outputs.
The art underscore, Arax, is the input through which the module receives the asynchronous surreal
data.
They both underscore great underscore signal input gives regular policies that are used to sample data
on the serial input.
The data output carries the eight bit value received by the module, the valid underscore data output
determines the validity of the value on the data output.
Then we define three static variables that will be synthesized into registers in harder, the first
one says the received data.
It's the second one acts as a counter to count the number of receive bits.
And the last one keeps track of the circuit state, then we define the temporary variables for a state
and beat underscore count registered.
Then we need the state machine to implement the module behavior.
After that, we should update registers and assign values to Doubt's, as I mentioned earlier, the
state machine has two estates idle and Rosie.
In the final state, the circuit is only waiting to receive the circuit.
When it receives a zero on the fourth and the score asks input, it goes to the receiver state to get
the data, it's in the receiver state if the board rate is zero.
It stays in the reserve state waiting for the next sampling time.
When the board right signal is one, it samples the art, our signal and says that in the dirigiste
and increment the count.
After finishing the database, it samples the subject that should be one, if it is one, then it activates
the valid data local variable and goes to the Iowa State.
Let's review the whole design, the basics, the board is connected to a computer through the you are
data USB port when we press a key in a surreal terminal program on the computer.
The corresponding ASCII code will be sent to the board to receive design inside the fridge, receives
the code and shows that on a seven segment display.
There is a design inside the FPGA consists of three epis.
The first on the main one is the receiver IP.
In addition, we need the both right signal generator and then IP to display and ASCII character on
a seven segment display.
Now let's go to the white Essentialists and designed ipis, the first one is a display of.
Open the white to and create a new project with the name of serial underscore display, Dasch want to
choose a serial underscored display as a design type function and select the basis to report as a target
FPGA platform.
Download the design, 5:00 a.m. to the creative project.
Open the design here, it contains an array of the same segment codes for characters from zero to F.
Because of the seven segment restriction in showing all characters, we only show these characters on
this one segment.
And for any other character, we shall see.
Open the design file, it receives an ASCII code and convert that to the corresponding seven segment
code.
The function askey to some segment, does this task synthesize the code and generate the corresponding
artier like.
Now, let's describe the yard, receive our invite to create a new White House project with the name
of your art underscore receiver dash.
White physicians choose the art on the receiver as a top function name and select the basis three board
as a target FPGA platform.
Download the design and test files and add them to the project's.
Open the design source file and inspect the design top function.
Then open the open source park, the main function calls are designed to function several times each
time a single bit of Dewart packet containing the ASCII code of the character is given to the design.
Now, let's perform the simulation and check out the output confirms the design functionality.
Now, we should perform the high level syntheses and generate the corresponding IP.
Now we are going to connect the lips together in Nevada project.
Create a new we, the project with the name of you art, underscore receiver dashboard and choose the
basis to report as a target FPGA.
Create a new blog design.
And at three ipis today, we want a repository.
All right, generator, surreal display, and you are receiving.
You can find some of the ipis in the resources folder attached to this lecture.
And ipis into the design area and connect them together.
Download the content fine from the resources folder attached to this lecture and add that to the project,
how we look at the conference, then generate the FPGA bitstream and program the board.
Run a terminal program on the computer that is connected to your board.
You can use the Terrytown program, go to the set up serial port, choose the proper comport corresponding
to your board.
Select ninety six hundred as they speak and keep the default values for other options.
Now, why the terminal program is running Presta a character.
You should see the character on the some of the segment on your board.
Note that the terminal doesn't show anything, however, you are using its API to communicate with the
receiver on the board.
Now, let's perform the runtime debugging to investigate the timing behind the data transfer between
the PC terminal program and the board, if you want to project and add the IP to the design.
We are going to monitor two signals you can't underscoring and the Boatwright's signal.
Our trigger condition is when the start, it appears on the chart, underscore our signal.
Double click on the IP there, customized IP window will appear.
In the general options to choose negative as the monitor type.
Then set two for the number of props.
Choose one hundred and thirty one thousand seventy two as a sample data depth, now go to the pro tab.
Select the data on trigger for the first probe and only data for the second probe.
Press OK, to close their customized IP window.
Now, make the connections, first of all, connect the clock signal, then connect the dots, connect
the zero to the earth, underscore our signal unproven to the border signal.
Then generate FPGA bitstream and programmed the world.
The hardware manager window should appear, go to the trigger, set up top and define the trigger boolean
expression for this purpose, click on the plus icon and select the only signal on the list.
We should start sampling when we receive a zero, and you are to underscore our signal, so change the
value to one to zero transition.
Now go to the setting tab on the left, make sure that the trigger position in window is zero.
Then in the south, stop, click on the wrong trigger for this L.A. icon.
Dialla Core is monitoring the art underscore IREX for the triggering condition.
Now, in the surreal terminal program, type the character A.
As soon as you type the character, Dialla receives the following edge on the art underscore arcs and
it starts the data sampling process.
You will see the signals on the way form viewer.
Check the waveforms and make sure that you understand the time.
As this video is the last lecture explaining how to design your transmitter and receiver IPIS in the
next lecture will give you a couple of exercises to master what you have learned throughout this section.
These are our takeaway messages.
It will stay there for them along with the counter can model if you are to receive our module in the
falling edge of the new earth, receive our signal can be used to trigger Iola for monitoring that you
are timing in inveigle.
Now, the police question monitored the data output port of the you are receiving IP during runtime
debugging.