How can we describe this amateur driver that implements the one face on this lecture will guide you
through the steps to design such a circuit invited such as?
As mentioned in the previous lecture.
In the one phase on stepping, only one phase is energized and the time, therefore the drivers signal
before has four different states, each only energizing one phase.
So a four state FSM can present the driver circuit.
As amateurs usually work at the higher current, then a system board can typically provide from their
large accounts.
Therefore, a harder driver should bridge between step motor and a digital world, such as the basis
three.
Here we use the PMA, the step from vigilent.
The other step can communicate with the basis to report via the GPO general-purpose IO protocol provided
by the Pimlott interface.
As does the promoter needs a five world power supply, we use an external five-fold module.
This picture shows the stepmother to set up that we use along this section.
This figure also shows the detailed connections between the people on the basis report the driver signals,
and that's what you can find the PM on the step and stop a motor manual and schematics on the Windows
websites.
Let's have a big picture of the design in the final design consists of two ipis to stop a motor driver
ipe and a step in motor generator.
Now, we should design our stepper motor driver invited us first, let's describe the step and more
to generate a circuit curtain to socialist project with the name of Stepa Underscore Multa underscore
Pol's dash, why the Socialists and choose their supper.
Underscore Malter, underscore Pol's as a design top function.
Don't forget to choose the basis to report as a target FPGA platform.
Download the design files from the resources folder attached to this lecture and add them to the project's.
Open the design stores, find the design is very similar to this single cycle regular Ponza Circuit
explained in the utility section, except here the Paulsboro is one million to create a one hundred
hertz single cycle clock frequency.
Synthesize the code and generate the corresponding IP.
Then we should describe the stop of driver implementing the one phase on metal.
Continue White Socialist Project with the name of a stepa underscore Motter, underscore driver dash
white researchers choose their stepa underscore motha underscore driver as a design top function.
Don't forget to select the basis to report and the target FPGA platform.
Download the design interspeech files and add them to the project.
Open the design source.
As the design has for states and enumeration data type defines them.
Then the design top function with two arguments is the point, the first argument is an input signal
that defines the motor Calexico.
The second argument is a four bit output that provides the motor driving signals.
Then we need a static variable to hold the design state.
This variable will be synthesized into a register in the final hardware.
Two temporary variables save the intermediate values for the state variable and the design on the output.
Now we need a state machine to implement the waveform of the one phase one method explained earlier
in this lecture.
Each state first checks the input motor clock.
If it's one, then it goes to the next state.
Otherwise it stays in the current state.
In addition, in each state, only one output bit is active.
Finally, we should update the state register and send out down to value.
Now, let's have a look at the testimony by.
Two NATO troops are used to call the design.
The outer loop contains 20 iterations in each iteration, it sends a pulse on the motor to the right.
The inner loop contains five iterations during which the multiclass signal is zero.
In summary, these Tunisa groups called the design several times.
Every five clock cycles, they generate one single pulse on the clock signal.
Let's perform the simulation and check it out.
D'Albert shows the to clucking signals, which confirms the design functionality correctness.
After performing the high level sentences, the synthesis report shows that the design follows the risky
design approach as the initiation interval is one.
Now we are ready for the archaeological simulation.
Please don't forget to select the all auction for the dumped rice feature after finishing the archaeological
simulation, successfully opened the way for the.
So the design, input and output signals, along with the design coxing, please ensure that you understand
the analogy between these waveforms and the one phase unmetered waveforms explained earlier in this
lecture.
Now let's explore the afterlife IP and get ready for logic syntheses.
For performing the logic syntheses, create a new Devinder project with the name of a Stepa, underscore
Multa, underscore driver Dasch, we want and choose the basis to report as a target FPGA platform.
A new blog design, then add to Epis to divide the repository.
Stop amort clock pulse and stop him Auto Driver IPD.
Then I types into the design area and connect them together, make the remaining port external and modify
the external port names properly.
Download the design consent for it from the resources folder attached to the.
And add that to the project.
Open the constant fight and change the motto name to motto on that score, signal in the constraint
under the Jayce one.
Now, generally, the bitstream and programmable.
The next lecture will explain the two phase unmetered in each of us to drive our supermoto.
These are our takeaway messages, stepper motors usually work at a higher current than the system both
can typically provide from their logic.
Therefore, a Honda driver should provide enough power and energy for the motor.
S Department of Driver in Etchells requires a pulse generator that usually should generate a frequency
of around one hundred hertz, this frequency determines the speed of the supermoto.
Now the question, why do we need an external five world power supply?