How can we describe the stop, a motor driver that implements the two phase one method, this lecture
will guide you through the steps to design such a circuit in why decisions?
As I mentioned earlier in the section, to drive a sleeper motor with two phase unmetered, we should
repeatedly apply this waveform to the state of the waveform has four steps.
Each step the to calls for a state FSM can model this behavior.
Let's ascribe to the state machine invited us.
But before that, let's have a big picture of the final design.
The design consists of two ipis, the first Sipes, the Supermoto driver.
That implements the FSM, as mentioned earlier, and the second i.p generates regular pulses that are
used for triggering state transitions in deficit.
Creating a White House such as project with the name of a Stepa on this underscore driver Dash White
Essentialists choose the supper on this Kamata underscore driver as a design top function name.
Don't forget to select the basis to report as a target FPGA platform.
Download the design enforcement files and add them to the project.
Open the design, Sourcefire.
As a design has for states and enumeration data type defines.
Then the design to function with two arguments is defined, the first argument is an input signal that
determines the motorcoach signal.
The second argument is a form without that provides the motor driving signals, then we need a static
variable.
To hold a design state, this variable will be synthesized into a register in the final HAGA.
Two temporary variables saved intermediate values for the state variable and the design only out.
Now we need the state machine to implement the waveform of the two phase on method explained earlier
in this lecture, each state first checks the input motor clock.
If it is one, then it goes to the next state.
Otherwise it stays in the current state.
In addition, in each state to output, bits are active.
Finally, we should update the state register and send out the output value.
Now synthesize the code and generate the corresponding afterlife.
For performing the logic syntheses, create a new view of the project with the name of Stepa underscore
to underscore driver Deshwal and choose the basis three borders target FPGA platform.
Create a new blank design and add to eyepiece to define the repository.
A Supermoto clock pulse and a supermodel right then and the ipis into the designer, you can connect
them together, make their remaining port excel and modify the external port names properly.
Download the design consent pie from the resources folder attached to this selection and add that to
the project's now general activities, Three-Month Program Board.
How can we control the number of rotating steps in the next lecture?
We'll answer this question.
These are now takeaway messages, and FSN with four states can implement the two phase one method,
the two phase one method energises two codes of the state's initial step.
Now, the quiz question, how can you find a stable angle in a motor specific?