1 00:00:01,420 --> 00:00:06,730 After having a big picture of the design steps in designing Savar, the suite actually select toolset. 2 00:00:07,800 --> 00:00:10,650 We should know this specific tool that performs is just step. 3 00:00:14,020 --> 00:00:19,900 We want a design suite, which consists of two main software tools like such satellites, and we've 4 00:00:19,900 --> 00:00:24,310 got the Etchells design for it starts with such software. 5 00:00:25,360 --> 00:00:32,590 This software gets your design description in C C++ and translates it into the equivalent HGL description. 6 00:00:34,070 --> 00:00:37,700 The White House, as the software performs five subtasks, including. 7 00:00:39,530 --> 00:00:47,660 Design capture, sea simulation as syntheses simulation and package generation. 8 00:00:48,790 --> 00:00:55,090 The generated package, or IP, should be imported into the world of design suite software for logic 9 00:00:55,090 --> 00:01:02,170 synthesis and then BitStream Generation Vivoda consists of five steps, including design, capture, 10 00:01:02,500 --> 00:01:08,590 RTL simulation, logic, synthesis, implementation and finally, bitstream generation. 11 00:01:09,340 --> 00:01:13,060 That generated bitstream can be used to program the target FPGA. 12 00:01:17,050 --> 00:01:23,430 Let's have a close look at the White House, such aside, after running the way to such a software and 13 00:01:23,440 --> 00:01:30,010 negative space, it appears on the screen the whole design is defined under a project which its a structure 14 00:01:30,040 --> 00:01:31,970 is represented in the Explorer review. 15 00:01:33,290 --> 00:01:40,310 The main part of the project structure is a source test folders, where you can add a new source file 16 00:01:40,430 --> 00:01:47,230 or delete an existing file from the project, a proper allows you to write your code and find the typos. 17 00:01:48,690 --> 00:01:54,720 All their tireless tasks can be invoked by clicking on the proper links in the menu or icons in the 18 00:01:54,720 --> 00:02:04,500 toolbar forming icons or corresponding to see simulation, syntheses, code, simulation, export, 19 00:02:04,500 --> 00:02:06,470 archil or IP generator. 20 00:02:10,480 --> 00:02:16,860 They generated IPE by White House should be imported into the Vivoda design suite for logic sentences 21 00:02:17,410 --> 00:02:20,230 without Idee provides a project based process. 22 00:02:20,650 --> 00:02:26,300 You can use Vlada idea to perform all tasks from design definition to the bitstream generation. 23 00:02:26,920 --> 00:02:30,610 The fellow Navigator Pane contains a list of all these tasks. 24 00:02:31,150 --> 00:02:36,190 The top section in the floor navigator is for changing the project settings, such as adding source 25 00:02:36,190 --> 00:02:42,580 files, divining the parameters of target of PGS, simulation, syntheses, implementation bitstream 26 00:02:42,580 --> 00:02:47,020 and lots of other features that we explain parts of them along the course. 27 00:02:48,410 --> 00:02:55,160 The second section I been decorator is used for defining the design of space and integrating degenerated 28 00:02:55,160 --> 00:03:01,480 ipe by viticulturist into the design, Darters simulation is accessible in the third section. 29 00:03:02,420 --> 00:03:08,570 Section four to seven are used for ARTlE synthesis, logic, synthesis, implementation and bitstream 30 00:03:08,570 --> 00:03:09,140 generation. 31 00:03:12,160 --> 00:03:13,270 Now, the question is. 32 00:03:15,370 --> 00:03:21,560 How can we install our software and hardware components and prepare our lab environment the next lecture? 33 00:03:21,730 --> 00:03:22,930 We'll answer this question. 34 00:03:27,780 --> 00:03:36,240 These are our takeaway messages to use C++ language to design hardware targeting Xining refugees, we 35 00:03:36,240 --> 00:03:39,930 should use two different software tools, White Essentialists and Vivoda. 36 00:03:41,760 --> 00:03:48,600 The White House, such as Convertor C, C++ description to the equivalent HDR code and Evandro receives 37 00:03:48,600 --> 00:03:51,570 the HGL code and generates the final BGB. 38 00:03:54,510 --> 00:03:59,880 Now the police questions, what are the design tasks in designing Sweitzer, such as software? 39 00:04:01,000 --> 00:04:04,440 What are the design tasks in designing Svindal software?