What is the basic memory, so in a typical FPGA in this lecture, I'm going to introduce you to the
smallest memory cell in the FPGA, which is the underlying component of all other types of memories
inside an FPGA.
As we learned in the previous course, combination of circuits are composed of basic logic gates and
perform the functional tasks without any memory storage.
However, some circuits and designs should save data or states temporarily or permanently.
These types of circuits are called sequential circuits.
The basic memory cell using in almost all Fijis is flipflop, which can save a single bit logic value,
a simplified model of a flip flop, accepts to input signals and generates an output signal.
The input signals are data and clock.
The output signal is the flipflopped state.
The data signal carries the next the state of the flipflop, but it cannot be saved in the memory until
the clock signal gives permission, this permission usually happens at the age of the clock.
Either off rising or falling EDG can give permission, and it depends on the type of the given flipflop
flipflop that receives the data input signal and activates at the edge of the clock is called the flop.
If you assume the rising edge, then at each rising edge, the value of D is saved in the flipflop as
its current state and is shown on the output signal.
In this timing diagram, we have two rising ages.
The first one put the value of zero and the second one put the value of one into the FILIPO.
A table can demonstrate the functionality of a deeply flawed.
As shown in this table, the rising age of the clock saves the data into memory.
To clarify the flip flop behavior, let's take an example, assume to flip flops that are connected
sequentially.
These are the clock and data signals.
We are going to find it to output signals.
Q1 and Q2, the rising age of the clock, runs the input data to the different floor and the first rising
edge and Q1 are zero.
Then the Q1 and Q2 should both be zero.
At the second rising edge, the D and Q one are one and zero respectively, then the Q1 and Q2 should
be one and zero.
And the third rising edge that the and Q one are zero and one respectively, then the Q1 and Q2 would
be zero and one finally at the last rising edge of the clock, the D and Q1 are one and zero respectively.
Then the Q1 and Q2 would be one and zero.
Now that we know how the deeply flawed works, the question would be how does a sequential circuit use
a memory cell in a typical FPGA?
The next lecture will answer this question.
These are the takeaway messages from this election, do flipflop is the basic memory cell inside an
effigy that can save one bit of data.
The flip flop requires the rising or falling age of the clock signal to save input data.
Now, the question, consider this design and the data signal, find a Q1 and Q2 signals or the time.