The clock signal plays a crucial role in the sequential circuit performance, however, what are the
characteristics of a clock signaling each us in this lecture?
I will explain the clock signal definition and characteristics inviter such as?
Let's consider the flip flop, as mentioned before, it saves the input data value on the rising edge
of the clock.
However, there are two timing intervals before and after the rising edge during which the data should
be stable and must not change.
The timing window before the edge is called set up time and the one after the edge is called whole time.
During this window slot, the flip flop sampled the data and says that into its state.
The duration of these times depends on the underlying technology implementing the flipflops, therefore
they are fixed and cannot be changed or controlled during the design.
Instead, the combination of all circuit generating the flipflop input should provide the data before
this window.
And keep the data unchanged during the flipflop sampling period.
Assume this simple sequential circuit, the flipflops are saving their data on the rising age of the
clock, let's assume in data is one killer is one and zero.
Now in data changes to zero before the rising edge of the clock.
And the rising edge, the first flipflop saves the data and changes the cue from one to zero.
The combination circuit receives this data and changes its output after its propagation delay, if the
set up on hold time constraints are satisfied, then the new logic value Ondes will be saved in the
second flipflop on the next rising edge of the clock.
In this example, there is a margin between the combination of circuit propagation delay and the clock
set up time, which is usually called exactly.
This means the clock could be fast.
However, for many reasons, such as reliability and uncertainty, designers prefer to consider some
margins in the clock timing.
In summary, a quiet period consists of two main parts combination logic, propagation, delay and uncertainty.
The clock on certainty is used for high level sentences, White House HLS uses internal models to estimate
the delay of the operations for each device.
The clock uncertainty value provides a controllable margin to account for any increases in net delays
due to archaeological Santos's place ungrouped.
Now, let's have a look at the clock signal setting inviter Cegelis, the fourth system of the create
new project Wieser invite Essentialists its solution configuration dialogue where you can define your
design parameters.
Two parameters are the clock period and uncertainty.
You should specify the clock period in units of nanosecond or as a frequency value specified with the
megahertz suffix, for example.
One hundred and fifty megahertz.
I specify the uncertainty as a value in nanoseconds or as a percentage of the clock per the default
clock, uncertainty is 27 percent of the clock period in.
Such as?
Collect signals, save new data in the memory part of a sequential circuit and transfer the design into
a new estate.
But what is a sequential circuit state in the next lecture?
I will explain the basic concepts of the states.
More details about the states and how to use them to design a sequential circuit will be explained in
a separate section.
These are our takeaway messages during the setup time and whole time they put up a flip flop should
be stable.
They didn't collect period in Etchells has two parts combination of circuit propagation, delay and
uncertainty, the default value of the clock uncertainty in white Essentialists is twenty seven percent
of the clock period.
Now, the question, if the propagation delay of a combination or circuit is seventeen point three nanoseconds
and if you assume the default uncertainty in the White House is what would be the minimum design clock
period?