1 00:00:01,600 --> 00:00:07,570 How can we describe a simple sequential circuit connecting a beautiful flopsy necklace, this lecture 2 00:00:07,750 --> 00:00:08,960 copes with this question. 3 00:00:11,080 --> 00:00:16,950 In this example, we are going to describe these thrifty flipflops connected together sequentially, 4 00:00:17,470 --> 00:00:21,490 the second has one binary input and three binary outputs. 5 00:00:24,430 --> 00:00:30,280 First of all, Ron, the White House and create a new project to create a new project, click on the 6 00:00:30,280 --> 00:00:33,790 Create Project Link in the White House welcome page. 7 00:00:34,340 --> 00:00:38,680 Then choose a project, name and location, for example, choose DFS. 8 00:00:39,490 --> 00:00:44,950 Why does such a list as a project name then for the top function name, enter DFS. 9 00:00:46,360 --> 00:00:49,750 Now you should select the Basis History Board as a target platform. 10 00:00:50,500 --> 00:00:55,450 Click on the ellipsis icon in the part selection section, then find the board and select that. 11 00:00:55,990 --> 00:01:02,080 Please notice that in the flow target section delivered IP full target option and select. 12 00:01:05,150 --> 00:01:11,300 We should create a design file under the source folder in the project for this purpose, right? 13 00:01:11,300 --> 00:01:15,830 Click on the source folder index for review and select the new file option. 14 00:01:16,340 --> 00:01:20,030 Choose a name for the file, for example, DFS, DOT, CPB. 15 00:01:20,720 --> 00:01:25,360 Notice that such a list create the file outside the project folder by default. 16 00:01:25,520 --> 00:01:30,920 So double click on the project folder to create the fine inside the project directory. 17 00:01:39,940 --> 00:01:45,580 After creating the design finds create a test by Sawsan Heather finds in the test bench folder. 18 00:02:00,570 --> 00:02:05,160 And the design had a fine first include the underscore in header. 19 00:02:06,410 --> 00:02:13,310 This project doesn't use this hydrofoil, but as we use this header file most of the time in this course, 20 00:02:13,310 --> 00:02:16,210 it is a good practice to include that all the time. 21 00:02:18,450 --> 00:02:25,260 And the design source file first include the header file, then defined the design top function with 22 00:02:25,260 --> 00:02:31,830 the name of the Effervesce, which has four boolean arguments, one input and three outputs. 23 00:02:33,060 --> 00:02:39,570 Then, as we should have three flipflops in our design, define three static boolean variables and initialize 24 00:02:39,570 --> 00:02:44,700 them to zero to connect these different flops together, we use normal variable assignments. 25 00:02:45,580 --> 00:02:47,760 Please notice the order of assignment's. 26 00:02:49,750 --> 00:02:52,930 First, we assign death to to death three. 27 00:02:54,170 --> 00:02:56,660 Then of one to death, too. 28 00:02:57,290 --> 00:03:01,010 And finally, we are seeing the input value to the former. 29 00:03:02,920 --> 00:03:06,820 Then we should assigned a static variables to the function arguments. 30 00:03:09,110 --> 00:03:13,910 Now we need to assign proper interfaces to the top function arguments. 31 00:03:15,140 --> 00:03:21,680 We use AP underscore, not interface for function arguments to implement them with simple wires and 32 00:03:21,680 --> 00:03:28,550 AP underscore Setara underscore none to the top function to ignore any module level control signals. 33 00:03:48,010 --> 00:03:53,920 Now, let's prepare the test benchmarks in the Test match, Gadaffi include the design header fine and 34 00:03:53,920 --> 00:04:00,610 the design top function prototype, then in the test by Sourcefire defined the main test benchtop function. 35 00:04:02,110 --> 00:04:08,350 Please recall that the main function should return zero if the design is correct and a non-zero value 36 00:04:08,530 --> 00:04:15,040 of the design test goes wrong, and we as designers are responsible for checking the design functional 37 00:04:15,040 --> 00:04:19,000 correctness, the status variable is defined for this purpose. 38 00:04:20,180 --> 00:04:25,970 Defined three boolean variables and called the design top function five times each time we choose a 39 00:04:25,970 --> 00:04:27,900 different value for the input. 40 00:04:27,920 --> 00:04:32,670 The also print the function arguments on the screen for inspection. 41 00:04:33,320 --> 00:04:36,290 Let's save the file and then run the simulation. 42 00:04:41,850 --> 00:04:43,350 Click on the simulation icon. 43 00:04:44,710 --> 00:04:50,890 If you don't have any typos in your code, then the results will appear on the screen, you can see 44 00:04:50,890 --> 00:04:58,060 that by calling the top function in the test bench D.F., samples of the input value and the other type 45 00:04:58,060 --> 00:05:01,120 of outputs are shifting one bit to the right. 46 00:05:02,130 --> 00:05:06,990 As can be seen, it's a function call needs only one clock cycle to finish. 47 00:05:09,300 --> 00:05:13,650 Now they can perform the sentences and generate the corresponding article code. 48 00:05:32,340 --> 00:05:38,220 After synthesizing the design successfully, the White Essentialists shows the sentence a summary report. 49 00:05:40,190 --> 00:05:45,800 If you would like to know more about the center's results, please have a look at the center's report 50 00:05:45,800 --> 00:05:52,070 folder, which contains a report filed for the top level function and one for every SORP function that 51 00:05:52,070 --> 00:05:58,640 has not been in line into a high level function by Wiktor, such as the report for the top level function 52 00:05:58,760 --> 00:06:01,430 provides details on the entire design. 53 00:06:09,920 --> 00:06:14,660 As can be seen, they design only utilizes three flipflops and nothing else. 54 00:06:15,770 --> 00:06:20,510 Also, all the ports are implemented as simple wires. 55 00:06:21,980 --> 00:06:28,670 As a second is sequential, there are two other signals in the generated article design clock and recent. 56 00:06:32,370 --> 00:06:35,250 Now, let's perform the artillery simulation. 57 00:06:39,440 --> 00:06:43,350 So the whole option under the dump trace feature and press. 58 00:06:54,790 --> 00:07:00,160 After finishing the simulation, click on the viewer IRC, the world will be opened. 59 00:07:06,510 --> 00:07:10,380 And you can examine the signals on the design inputs and outputs. 60 00:07:22,120 --> 00:07:29,920 As can be seen on the rising edge, the binary value and the input is passed into F1 output and other 61 00:07:29,920 --> 00:07:32,770 DF outputs are shifted to the right. 62 00:07:44,530 --> 00:07:49,840 In the previous lectures, we learned that the multimedia static variable can be mapped to a register. 63 00:07:50,530 --> 00:07:56,740 Now the question is, how can we use a multiple static variable to implement the connected D.F. example 64 00:07:56,740 --> 00:07:57,890 explained in this lecture? 65 00:07:58,930 --> 00:08:01,060 The next lecture will answer this question. 66 00:08:04,940 --> 00:08:06,560 These are our takeaway messages. 67 00:08:07,160 --> 00:08:13,010 This is of connected, the flipflops can act as a shift register that shifts the data to the right on 68 00:08:13,010 --> 00:08:14,480 the rising edge off the clock. 69 00:08:17,500 --> 00:08:24,790 Now the question, how to modify the project parameters to remove the reset signal from our design and 70 00:08:24,790 --> 00:08:25,870 implement this Sakar.