The register is a set of flipflops with the shared control signals such as clock and reset signals,
how can we describe a scene and HLS code?
This lab answered this question by implementing the same design example explained in the previous lecture.
Our design example in the previous lecture consisted of three flipflops connected together as a shift
register.
Here we are going to describe the same design using a multiple static variable notice that usually the
most right bit is the least significant it and is denoted by index zero.
Consequently, the most right bit is the most significant bit and is denoted by index and minus one
square and is the number of bits in the variable.
First of all, let's create a new White House project with the name of DFS under a school register.
That's such.
Choose the basis three board and the target the platform.
Make sure that we want IP floor target is selected under the floor target.
A design source and interface also create a New Testament source and Weatherford's make sure to save
the files inside the project folder.
In the design there, fine include the AP Underscore Edge in the design Sourcefire first include the
header file and then define the top function with two arguments defining a static variable of type API,
underscore you into three and initialize that to zero, then shift unregister content one bit to the
right more hour at the input data into the mouthpiece of the register.
In the end, I signed the register to the argument, let's add the port interfaces later and see what
would happen.
Now, we should try to test match code, open the Test match header file and include the design header
file and then add the design top function prototype, open the test open source file and define the
main function, define the status variable and return that as usual.
Then let's call the design top function several times with different input values.
Note that as our goal in this test bench is viewing the design output waveforms.
We have not checked the results and the test bench always claims that the design is correct.
Now we can simulate our description.
The output confirms that the right shift is performed in the design.
Now, let's synthesize the code.
Let's look at the full synthesis report.
We can see that the hardware design uses for flipflops among which tree implements the state variable,
and one is for control purposes generated by the synthesis to.
As we haven't explicitly defined the port interfaces, the HLS tool has considered their default interfaces.
I will talk about these interfaces later in discourse now let's add the design interfaces and synthesize
the code again.
To see the sentences waveform first, we should run our TLC code simulation, please make sure that
you have selected all Allport in the dumps resorption.
After finishing the article, Zikos Simulation, click on the Open Wave.
Do we want away from viewer will appear?
Shoddy design put an end to the arguments as well as the clock signal.
Check that the design outputs are shifted to the right.
As this video is the last lecture in the section that explains IDF concepts in the next lecture will
give you a few exercises to review what you have learned throughout this section.
This is our takeaway message.
A multiple static variable can be used to describe a shift register in an Alesco.
Now, the quiz question design a sequential logic circuit in Etchells that describes a four bit shift
register that performs the left shift and accepts the new input as its LSP.