In this lecture, we are going to design a circle to parallel Converse.
We will follow the same design approach used in the previous lecture based on the single cycle design
technique.
A surreal parallel convertor receives a stream of data sequentially and saves that in a multi bit register
and sends the parallel data out at the end of the conversion.
For example, if the circuit received the sequence value of one zero one zero zero one one one, the
output would be one one one zero zero one zero one.
We also consider an input signal called start and then output signal called end.
Duvalier won on the start signal commands a convertors to start the conversion.
The signal is activated when the last bit received and the parallel output is available and valid,
this timing diagram shows the behavior of the final design.
The pulse on the start signal indicates the arrival of the first.
Then second counts to receive eight meets and keep them in internal register.
When receiving the last bit, the received a data can be accessed on the design output and the end signal
goes to one.
Let's write this code for the serial to parallel convert, the function has four arguments to inputs
and outputs.
We should define three static variables that will be synthesized into registers in the generated article
code.
The first variable called aState Underscore Regg will hold the received data.
The second one, named AI underscore underscore out, holds the output value and the last one will keep
the number of receive its.
The first two variables are initialized to zero and the last one is initialized with.
We also define two arrivals to save the next value of the counter and the state underscoring, let's
call them next underscore counter and underscore state respectively.
Later in this course, I will explain the idea behind these 10 priority variables in a dedicated section.
And if a statement checks the start, underscore serial, underscore data signal, and if it's one,
it assigns zero to the next underscore counter valuable, ready for receiving their serial data.
The next, his statement checks, the next underscore counter value to receive data if the next underscore
Cantor is less than N minus one, there are data is shifted into the next underscore.
A state variable was the end on the score.
Conversion output is zero.
The next underscore counter is incremented in this case.
If the next underscore country is in minus one, then the rest of it is shifted into the next, underscore
a state variable as a last bit.
The next underscore Kountouris incremented and the end underscore conversion signal is asserted to one.
In addition, the final parallel data is set to output through the underscore underscore outrageous.
Finally, if the next underscore counter is greater than N minus one, the second does not accept any
receipt data.
After finishing the statement, the value of temporary variables should be assigned to the corresponding
registers, notice that the next variable data is received.
If a underscore Sariel underscore data signal becomes one again.
This diagram shows the structure of our design.
Please note that the sequential circuit generates two types of outputs to underscore convergent output
signal is generated by the combination of circuit directory and the output is driven by a register.
We should pay special attention to the output signals generated by the combination or circuit directly.
Let's explain that in a separate slide.
Doubt produced by the combination of circuit directly might be the subject of glitches, if in that
particular application glitches are not acceptable, then the output should be derived by a register
or a flipflop.
Glitches are transient voltage or current spikes that corrupter signal.
Their occurrence is illustrated in this figure, which shows a simple and gate generates output.
When any input is low, the output must be low.
However, depending on the propagation delays, B might arrive after A causing a glitch to occur.
And why?
One solution to avoid glitches is using flipflop or register to save the intermediate values and then
drives the output signal.
In our design, we use such a register for the aout.
In order to evaluate our parallel to surreal and surreal parallel design and action, we should connect
a few hardcore IP modules together.
Actually, in a general case, designing sequential logic circuits usually requires a few hardware modules
work together.
How can we integrate several ipis generated by Etchells in the revised idee to design a complex system?
Answering this question is the goal of the next lecture.
These are our takeaway messages.
The single cycle design approach can describe a surreal to parallel convert.
A sequential circuit can generate two types of output, one is generated by the combination of circuit
directly and the other is driven by a radius, the output produced by the combination of circuit darkly
might be the subject to glitches.
Now, the quiz question describe a sequential second initialised to convert a 16 bit surreal data to
a 16 bit parallelled it.