How can we evaluate our parallel to surreal and surreal, to parallel designs and check their functionality
and practice this lecture, we'll handle this question using what is such?
And we want to design it.
In order to evaluate our designs, we synthesize them separately using white Essentialists and generate
the corresponding arc.
Then we integrate them and Nevada project and connect them together.
First, then you want a socialist project with the name of parallel to Sario Dash Livaditis.
Choose parallel to serial as a design top function name to the basis three more at the Target FPGA platform.
Make sure that if we want an IP flow target is selected as the floor targets.
Create the design and test bench finds as viticulturist creates the fires outside the project folder
by default, make sure to create the finds inside the project folder.
Upon the design, Heather find and include the AP underscore that Heather.
Then define the macro end, which is equal to it now open the design source file and include the Hanafi.
Then the design function that accepts five arguments, two inputs and outputs.
At the port, interfaces define a static variable called count and initialize that with that.
Then check the input, begin, if it is one, then assign zero to count, ready to convert parallel
data to Sario, then through a chain of, if else statements implements the functions behavior, as
mentioned earlier in this section.
Open the test, ban Sharafi, include the design header file and the design top function prototype.
Could be the parallel to Sariel Dash TV that five content into the test page Sourcefire, you can find
this file in the resources folder attached to this lecture.
I will explain how to write a test bench file for a single cycle design flaw in a separate section.
Let's just have a quick review over this test bench by the top function is called at line 18.
While the design signal is zero, then the design does not do anything.
Then the design is called eight times.
Why are the fall line 21 notice that only through the first call.
The begin signal is one.
So the designer starts to convert the input parallel data into serial data and sends one data point
out during each function called the if statement at the line twenty eight checks the design functionality.
Now we can perform the simulation after finishing the simulation, check the outputs if it is equal
to the input panel data.
Now perform the synthesis.
Have a look at the analysis perspective as it proves the single cycle article description for our analysts
code.
Let's look at the full synthesis report.
Detailed design consists of 33 flipflops and 151 one lookup tables, and all ports are synthesized into
simple wires as a design is sequential.
The clock on reset signals are added to the final hardcore.
Called RTL Siecle Simulation, select all option in the dumped race feature.
After finishing the simulation, the open view icon will click on that to open the all the way from
the.
Sure, the design input output clock and reset signals and check their waveforms.
Now export the corresponding yorgi.
We should also generate the we want IP corresponding to the therriault to parallelled circuits, so
create a new wireless such as project with the name of serial to parallel.
That's why to such a list, choose the basis to be born as a target FPGA platform.
Download the design and test bench files from the resources folder attached to this lecture, then add
them to the created winter such as project.
Investigate the design parts.
Have a look at a test by Sourcefire to follow Bodyline 21 called the design function eight times only
during the first call.
The start underscores, underscore, underscore on underscore data signal is one that indicates the
start of conversion after the eighth function call, then conversion should be one and then the output
is valid.
The test bench also compares the parallel data generated by design with the original data, and if they
match, the test would be successful.
Called the synthesis process, inspect analysis perspective and ensure that the description is a single
cycle Ortel design.
Now perform the artillery simulation.
Don't forget to select the all option for dumb trace feature.
Click on the Open Viewer IRC.
And if you want to wave your sure, the design, input, output and clock signals, please check the
generator parallel data at the eight o'clock cycle after the positive pulse on the surreal underscore
start signal.
Now, generically, we want IP by running the export archil task.
Now, we should connect the generated IPS together and check our design on the basis rebought.
For this purpose, created what the project with the name of parallel to Sariel to parallel Dashwood
to the base, is to report as the underlying FPGA platform.
Create a new black design, then add the generated IP into the Viviendo repository.
Now, find the IPIS and add them to the design area.
Connect IP together and make the external inputs and outputs change the external port names Ashong.
Now we need a set of physical constraints to connect the external power to the proper FPGA pins, you
can find the constraint fight in the resources folder attached to this lecture.
Right, click on the concentrate folder and select add resources then in the ad resources page ensured
that the ad or create constraints is selected.
Then click on Create File Bottom and choose the parallel to Sariel to parallel as the filing.
Open them to concern fines and face the constant fire content that you just download.
Have a look at the news constraints.
Now, right, click on the design and create the article wrapper, then run the generator out to products
task.
Following that, click on the generate bitstream link.
After generating the FBI bitstream program, the board and examine the design.
The design reads eight slide switches in power and converts them to serial data and it turns them back
to power and shows them on eight eles.
To start this task, you should press the push button whenever you change the switch is a status.
This video was the last lecture explaining the design ideas in this section.
So the next lecture will give you some exercises to master what you have learned by now.
These are our takeaway messages, a complex sequential design can be represented by a data photograph
in which each note can be an IP generated by the toolset.
They've evolved ideas can easily build the dataflow of an intricate design by connecting IPIS together.
Now, the police question connect to 16 bit parallel to surreal and surreal, two parallel ipis in Rebadow
and generate FPGA bitstream.