How can we run to cities for the single cycle parallel to sell your circuit explained in the previous
section?
This letter will explain how to write this Test match.
To show your circuit explained in the previous section, receives two inputs and generates three outputs,
a single cycle pulse commands the circuit to start the parallel to Cirio conversion, and it takes eight
clock cycles to send out an eight bit data.
The proper test bench should enable us to evaluate the circuit in each clock cycle.
As we know, each execution of the circuit based on the single cycle design approach takes one color
cycle to finish.
So if we call the design function in the test bench, fine, we expect one clock cycle of simulation.
This feature of the single cycle design approach helps us to have a second accuracy simulation that
is not available under other design techniques.
Let's show that for the panel to Serializer.
Anticipation starts with the sea main function.
As usual, we define this not as viable to represent the correctness of the design.
We should also define the variables used along the Test match code.
Now we can assign proper values to the design input arguments and then call the design top function.
Call runs a design once, which takes one click cycle in the single cycle design technique, known that
only calling the design top function advances the simulation clock.
So assigning values to variables is done in zero.
Simulation three.
During the first call, the design does nothing as the beginning input signal is.
We can then assign the value of one to the biggest signal and command of design to start conversion.
We should remember to write zero to the design signal after one design function.
This process ensures the creation of a single cycle pulse on the beacon signal.
Also, we can read the output signals after the design function call.
We can repeat the function.
Call as many clock cycles as we want.
Here, a forum called The Design eight times, then we can check the results and modify the status variable
appropriately.
In the next lecture, we will develop a test bench for the serial to parallel circuit explained in the
previous section.
These are our takeaway messages.
Considering the single cycle design techniques, each designed to function called in a test bench,
takes one simulation clock, other statements in a test bench do not take any simulation clocks and
will be done in zero time.
Now, the question down of the parallel to serial code, which is in the resources folder attached to
this lecture and examine the simulation as well as the artillery code simulation waveforms.