Artillery simulation provides a cycle accurate simulation for a design in Etchells, however, what
types of variables can be seen in the waveform?
Viewers using the surreal to parallel design example explained in the previous section.
This lecture will address this question.
The surreal to parallel circuit receives a sequence of bits and transfers them into the equivalent parallel
binary data, it receives one bits in each class cycle.
Let's consider an eight bit data.
Then on each rising age of the clock, a data, it appears, under the.
A one second pulse on the start input indicates the start bit of the sequence after the rising edge
of the eighth clock, the parallel data appears on the output.
Let's find a Test match, could we start with the C main function and define this not as variable?
Then let's define all the variables required during a Test match coat to call the design, we should
assign proper data to the design top function input arguments.
If there starts, very old data is zero.
The top function is simulated for one clock cycle, but doesn't do anything useful.
Now, to provide surreal data and start the conversion process, we should assign the value of one to
the start signal for one clock cycle and on each clock assign one piece of data to the input, starting
from LSP.
We can do this process using a full.
Then we can exit from the loop when the conversion finishes and finally check the result with the golden
model.
Now, let's synthesize and examine the results invited, such as idee.
Creative writers such as this project with the name of surreal to parallel dash writers such as.
Don't forget to choose the bases to report as a target FPGA then include the design and test range finds
you can download the files from the resources folder attached to this lecture.
Performed a high level syntheses and after that performed the artillery simulation.
If you have changed the code, you will be asked to synthesize your design again.
Don't forget to choose the all option for the dumped race feature.
After finishing the Article six assimilation process.
Click on the open vapor icon, the wonder wave viewer will be opened.
So the design, input and output signals, as well as the design clock and recent.
I think some designs, internal notes to the waveform viewer helps the debug process after syntheses.
For this purpose, click on the air, yes, underscore in underscore serial two part of the link in
their scope tap on the left.
And choose your desired internal object from the least in the objects tab in the middle, you can find
all the registers in the design that have been survived after high level syntheses here.
For example, choose the state, underscore Regg, underscore preregister note that the name of registers
or other nodes in the design may have been changed slightly.
Right.
Click on the desired object and select Atabay window.
The state register waveform will appear in the window now.
Right.
Click on the counter register and add that to the waveform as well.
To make the values in the counter more readable, you can change the right mix of values to sign the
simple.
You can also add other objects to the way window if you wish.
Now we can use the very forms to follow the design behavior, as can be seen, the single cycle pulse
on the serial start input, it starts the process and on each rising edge of the clock, the circuit
receives an input and changes the state and council registers, and it finishes the process after receiving
eight database.
To test some circuits during simulation, we should apply several data to their inputs.
These data can shape a signal why for now, the question is how can we generate a given input waveform
in a test which the next lecture will answer this question?
These are our takeaway messages and some of the design internal notes and registers to the waveform
viewer provides a better debugging environment for our TLC call simulation.
Servite registers after high level sentences are good candidates to look at their waveforms for debugging
purposes.
Now, the quiz question in the last waveform explained earlier in this lecture, Why have the states
register and the counter value changed one clock cycle after changes under the input?