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How can we create a given wave form as a test vector for an input of a logic circuit inviting such a..

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Sometimes we need to create a specific waveform for a logic socket input to test its functionality and

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timing.

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For example, assuming we should generate a single cycle pulse every four hundred nanoseconds to test

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the design.

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To focus on generating away from signals in a test bench, let's consider a very simple logic design

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that connects its input argument to its output when they enable signal is one notice that if you simply

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connect the input to the output, the description is synthesized into a combination of circuit, a simple

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wire, which is not desirable in this election.

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I have used the register called State in the description so it will be synthesized into sequential circuit

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with the clock signal.

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Let's assume the design clock frequency is 100 megahertz.

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As the first example, we should generate a regular single cycle pulse with the period of 80 nanoseconds,

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the pulse rate is 10 nanosecond, which is one clock period.

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The input signal is in a state one four one clock cycle and seven cycles in the state.

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In summary, one period of the input signal takes eight clock cycles.

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Let's try the test punch code to generate such input for our design under test.

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After including the required header files and the function for site we define to macro's and an M which

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are 10 and eight respectively, each input signal period requires eight clock cycles and we will generate

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10 periods of the input signal.

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The main function returns the status variable, which is zero all the time in this example, then we

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should define a few variables corresponding to the design top function arguments.

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In the first function called Let's pass a zero value to the design, remember that each function call

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takes one clock cycle as the design is based on the single cycle design scheme to generate one period

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of the input signal, we should call the design eight times in which only during the first call the

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input is one if loop can implement this condition.

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To repeat the signal period 10 times, if all loop can be used and compassing the aforementioned as

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it's in, therefore this code fits the design under test with the required periodic signal.

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After synthesizing the code and performing the art, you'll see code simulation, this diagram shows

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that signal timing, which is exactly the one required.

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Now, as a second example, let's generate the following signal as a design in one period of the signal

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contains eight of.

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Each bit lasts for 20 hours.

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The data in one period is one zero zero one one one zero one again, the design clock frequency is one

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hundred megahertz.

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We have a test match code similar to the previous code.

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We can define an area to say the data pattern in one period of the signal, then we can call the design

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function and send input data using this area.

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We should notice that each data elements duration is 20 nanoseconds, which means to function calls

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as each function call takes one clock cycle, which is 10 nemecek.

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After synthesizing the code and performing the RTL simulation, this diagram shows the signal timing,

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which is exactly the one required.

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This video is the last lecture in this section.

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Therefore, the next lecture will give you a few exercises to practice what you have learned throughout

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this section.

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These are our takeaway messages that can generate given away from signals for the design designing,

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considering the single cycle design approach, the number of function calls directly determines the

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number of times that an input data are applied to the design during simulation.

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An area that saves the input away from data can be used in a statement to be applied to the design under

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test.

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Now, the quiz question right at this point to apply the following to my form, to the input of the

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simple design proposed in this lecture.