In the previous lecture, we developed a combination lock controller in Nicholas.
Now, the question is, how can we synthesize and develop death invite to such as this lecture will
address this question.
Our combination look at this description in the previous lecture had two ports, the input and the door
open out.
In order to test our circuit on the basis report, we are to order inputs and two other outputs to description
the one with ENTA input determines the validation of the number on X input.
In other words, this input tells the state machine that the input data is already invalid and can be
sampled.
Two groups of Output's drive a seven segment display to show a number corresponding to the index of
the circuit state.
This table shows the number shown on seven segment display corresponding to each state.
These outputs are added only for debugging purposes and for understanding the circuit behavior.
The one with lock input closes the open door, actually, it resets the state machine and puts that
in a state as zero.
To give new input to the design, we can connect the input to slide switches on the basis of report
and enter input to a push-button.
Then whenever we change the X value, we press the push button, which will give a single cycle pulse
to the design.
When the design finite state machine detects a single pulse on the enter input, it reads the X value
and changes the state appropriately.
Let's develop our design.
Invite the specialists.
Creating a white essentialist project with the name of combination underscore luck dashed by the socialist
choose combination, underscore luck as a top functionary, choose the basis to report and the target
FPGA platform.
Download the design and test bench fines from the resources folder attached to this lecture at the fines
to the project.
Let's have a look at the.
Open the design header file after including the required Heather finds an array containing the seven
segment codes from zero to nine is defined.
The design fine utilizes an enumeration type to define the design the states, then it's a function
called get underscore seven underscore segment underscore code returns, the seven segment code corresponding
to a received number.
Then there is a design top function.
Which receives three inputs and generates three hours.
First, we define a static variable representing a hardware register which holds the design state.
We also define the corresponding variable to keep track of all intermediate values for this state throughout
the code.
There is also a variable that holds all the intermediate values for the door open outward argument.
Now we should define the statement.
It contains five states.
It starts at the S02 state whenever the signal is one, it reads the value on X and changes the state
if it's to the input and will also be checked in other states before reading the value on X.
Only in the last state in which the door is open, the state machine checks the lock input to lock the
door and goes to the zero state.
The testimony hydrofoil includes a design header fine and defines the design prototype, the test bench
main function sets different value on X and activates to enter signals to give a proper sequence to
the design.
Please have a close look at the lines.
Now let's perform the simulation.
The output represents the state transitions after calling the top function with proper input data.
After performing the high level sensors, the analysis perspective confirms the single cycle design
a scheme.
Now let's perform the RTL CECO simulation.
Don't forget to select the all option for the down price feature.
After finishing the RTL school simulation process opened the wavier.
And show the design, input and output signals as well as the design Calexico.
Now check the state transitions.
In the last state, that is two, three, four, six, the door is open and the door is open until we
activate the lock input signal.
I know that you may have noticed some slight glitches on some outfits.
First of all, these glitches are very tiny and don't impact the function behavior.
It seems some simulation structures behind the scene calls these glitches.
After checking the design behavior and timing, now we should export the RTL IP ready for logic synthesis.
In the next lecture, we will instantiate our generated IP interview via the project to perform the
largest synthesis and program, the basis to reward for playing with our design.
This is our takeaway message, adding some design internal signals and registers to the top function
arguments can help to better understand the design behavior.
Now, the quiz question trying to find a reason that causes the glitches on the output waveform in the
article, simulation output.