How could design a digital circuit for counting a sequence of events?
This section will call for discussion.
A counter is a device that can counter sequence of events or objects, a digital counter usually counts
a sequence of pulses.
Therefore, if a sensor converts the sequence of objects or events to a sequence of pulses, the digital
counter can be used.
A synchronous counter receives the clock along with a set of inputs and generates a set of outputs.
Inputs can be reset that sets the counter to zero enable that allows or inhibits counting direction
that determines whether the counter will increment or decrement data.
That is a parallel input data, which represents a particular counter value load that copies parallel
input data to the count.
There are several types of counters here.
We are going to design a single digit VCT up counter that receives a pulse and generates signals for
a seven segment display, regardless of the pulse with the counter increments, the output when it receives
the pulse.
The counter counts from zero to nine and then gets back to zero.
Creative writers such as Project with the name of Counter Dash, White Essentialists, selective basis
to report as the FPGA platform, then create to design files and to test bench finds.
Open the design header file, include the AP underscore in that file and define a constant array containing
the seven segment code for digits from zero to nine.
Save the file and then open the design source file.
Our counter should detect a pulse on its input so it should first detects the transition from zero to
one and then increment the counter.
It should then detect the transition from one to zero and get ready for the next pulse on the input
signal.
Therefore, the design has to estates, let's call them, wait for one and wait for zero.
This design has one input and two outputs.
It's a good practice to define the argument interfaces.
Right now we need to define two registers, one to give the current number of the counter.
And the second to keep track of the circus states, then corresponding to each register, we define
a variable.
Now let's define the two each case to describe the FSM transitions.
The switch statement has two cases corresponding to two states.
Initially, we are in the wait for one state when the count button is one.
We commend the next number of valuable and go to the wait for zero state, otherwise we stay in the
wait for one state, in the wait for zero state.
As long as the input is one we stay in that state when they are level zero is received.
The FSM goes to wait for one state ready for the next input pulse.
Then we should modify the registers and send out to some segment code corresponding to the counter number.
For this purpose, we can call to get someone segment code function.
Open the test bench, Khaddafi, and include the design header file and the design top function prototype.
Opened its main source file and include acquired Weatherford's then defined EMAP between seven segment
code and the numbers between zero and nine.
We use this map to decode the seven segment code to have more readable output on this screen.
Then right, the main function and define the status variable and return that.
Let's define three variables corresponding to the design function arguments.
We can use a for loop to generate a few pulses for the design and then we use two more for loops to
generate wider pulses.
After writing the code, let's perform the simulation, check out what you can see, that the counterinsurgents,
when it receives a positive pulse on its.
Now synthesize the code and look at the analysis perspective, the design as a single cycle, sequential
second.
That's far from the ideal school simulation.
Don't forget to dump all signals for inspecting their weapons.
After finishing the simulation, click on Open Viewer IRC.
Do we want the way we will be opened?
Showed you the input output and signals.
To show the signal wave form of the internal design registers, select, yes, underscore, underscore,
counter and a scope tap on the left, then right, click on the desired register or signal in the object
tab and select add to wave bingo.
The desired signal should be shown in the waveform window.
Let's at number understate registers to the waveform window.
Please check that with each pass and input the Kountouris increment.
Now, let's export the article IP to be U.S. in on the project.
Create a new Virata project with the name of Counter Daneshvar.
Don't forget to choose the basis to report as a target FPGA.
Create a new black design.
At the counter and the bouncer ipis to the Vivaldi repository, I'm not a piece of the design area and
connect them together and make the external parts.
Change the name of ports if you wish.
Cowritten, you can't and under proper constraints, you can find a list of constraints in the resources
folder attached to this lecture.
Now create the ideal rapport and generate FPGA bitstream.
Finally, program the board and examine the counter on the board.
How can we generate a signal with a given period?
The next lecture will cope with this question.
These are our takeaway messages, a counter is a digital circuit that counts up or down when it receives
a pulse on its input.
We need the bouncer to connect the mechanical switch to the input of a counter.
Now, the quiz question, modify the counter description such that it can count up or down.