FPGA boards usually provide the high speed clock signal, however, in some designs, we need a slower
clock signal.
Now, the question is, how can we generate this lower class signal based on the highest bidder bid
FPGA O'Rourke, this section will answer this question.
The idea of generating a slower clock with a frequency of slow from a fast clock with the frequency
of fast is using a clock division circuit.
Therefore, if the design clock frequency is a fast, then we can divide the frequency by 10 to generate.
For example, if fast is one hundred megahertz and is 1000, then flow is hundred kilohertz.
This diagram shows the relation between the design signal and the output of the clock generate or clock
during.
As can be seen, the output signal has to logic levels zero and one, our circuit also has two states
corresponding to these logic levels the circuit, the states in each state four and divide by two clock
cycles and then goes to the next state.
Now, let's try the code for a generator circuit that generates five megahertz signal from 100 megahertz
design clock.
In this case, and is one hundred divided by five, which means 20.
The of the designed clock is 10, 10:00, therefore, the period of the generated clock would be 200
nanoseconds.
The clerk's duty cycle is 50 percent, if it is in the logic level, one half of it's.
For writing the actual code, create a new White House project with the name of Klok underscore generator
dash want to select the clock underscored generator as a design top function.
Don't forget to choose the basic storyboard as a target FPGA.
And the design source folder create a design source and Heather Fart's also create the test bench in
the test bench for.
Upon the design, Sourcefire and defined the clock, underscore frequency, underscore deviser, macro
and enumeration data type that contains the circuit states which are zero and bar.
The design to function has only one output argument let's define the interfaces now.
We should define a register to represent the sum of the states, let's initialize that with zeal.
We also need to register with the name of counter that keeps track of clock cycles, and its initial
value is one less than half of the clock frequency devi's.
Following our single cycle design flaw, we should define two temporary variables to keep the counter
and the state's intermediate values in the circuit state machine.
Also, we need a temporary variable corresponding to the output argument.
Now we can use a two state state machine to describe the behavior of the circuit.
The state represents the time that the output is zero and the one state represents the time that the
output is one.
The country states half of its period in each state, the county register helps to keep track of the
number of cycles in each state.
When the circuit is in zero state, it decrements the counter on each clock cycle and when the counter
gets to zero, the circuit goes to state one while the counter is set to one less than the half of the
counter frequency.
The value.
The same behavior happens when the circuit is in a state one.
After the state machine, we should modify the registers and update the.
Now, let's try to test code.
OpenNet has been shattered by another design, top function prototype.
As we use the circuit for generating the output clock signal, the test bench file only calls the design
one hundred times.
Now we can perform the simulation.
Downwith, printed on the screen, shows that the second output is ten times one and 10 times zero.
This means the frequency of the output is one twentieth of the designed frequency.
Now perform the high level syntheses task and check that the description is synthesized into a single
cycle RTL code.
After finishing the sentence, he successfully performed the archaeological simulation and selling all
for the country's future.
Now click on the Open Viewer IRC.
Delivered away from the air will be opened.
Showed the second output signal and Checketts Pariente.
For triggering some circuits, we usually need a single cycle pulse, how can we generate a single cycle
pulse in the next lecture?
We'll address this question.
This is our takeaway message, using a collective either circuit, the kind of scale, the designed
frequency to generate a slower clock.
Now, the quiz question, if you check the revised away form carefully, you can see that the recent
signal doesn't have any impact on the circuit act, modify the project setting to reset the circuit
output with the designers that signal.