How can we generate a single cycle, regular pulses with a given period?
This lecture will cope with this question.
The single cycle regular generator receives a clock with the period of and generates another clock with
the period of TP in which the high state is only one cycle of the input clock.
And denotes the number of design or input clock cycles that fits in a period of the output clock.
And it can be calculated by dividing the TPE to take the output signal should be in the high level voltage
for one clock cycle.
And it should be in the low level voltage for N minus one clock cycles.
Let's write the code, we assume there are 20 clock cycles in the output pulse part that is and is 20.
The circuit has two states, zero and one corresponding to the output clock logic values, the design
of function has one argument, which is the output node, that the design clock will be added to the
circuit by their is to.
We should add port interfaces.
Now we need a static variable synthesized into a register to save a design state.
Also, we did a static variable to count the number of input clock cycles, according to our coding
style, describing a state machine.
We need a temporary variable corresponding to each register that keeps track of intermediate values
for registers throughout the state machine.
Similarly, we define a temporary variable for the output.
Now we should describe our state machine and after that, the registers and the output ports should
be updated.
The state machine has two states, the second should be and minus one clock cycles in the 08 state and
only one caucus cycle in the state as can be seen, the 08 state starts the counter from polls underscore
period minus one and decrements that on each clock cycle, when the counter is one, the state machine
goes to state one to spend one clock cycle.
Then it goes back to the zero state.
Let's check the design, invite Satchel's.
Create a new White House project with the name of single underscore cycle, underscore, regular, underscore
Pulsers Dash Wiki suchness.
Choose the basis three as a target of.
Download the design and test bench fines from the resources attached to this lecture and add them to
the project's.
Now, let's have a look at the coats we saw the design Sourcefire earlier in this lecture.
The test bench phone calls are designed to function 100 times and print the output argument on the screen
each time.
Now we can perform the simulation.
Know that our design follows a single cycle design approach, the result shows that the output signal
is zero for 19 clock cycles and is one for one clock cycle on each part.
By synthesizing our code, we can make sure that the result of the article description is a single cycle
designed for this purpose.
Please have a look at the analysis perspective.
Now, let's part on the R TLC simulation.
Don't forget to select the all option in the dumped race feature.
After finishing the simulation process, click on The Open Viewer.
So the design out to Don Clark signals in the event of a viewer.
And check the output signal, period and pulse.
How to detect edges on an input signal, the next lecture will answer this question.
This is our takeaway message, using a counter can help in some designs to determine the number of clock
cycles that a state machine should stay in each state.
Now, the quiz question modified the code in a single cycle, regular pulses, top function and generate
the following signal.