See simulation and RTL simulation work to debugging approaches we usually use during high level syntheses
designed for.
But how can we debug our design on the board at runtime?
This section will explain how to use an integrated logic analyzer IP to perform this task.
This section's main goal is to introduce the integrated logic analyzer LRIP in reverse order to monitor
design signals at runtime while the circuit is running inside FPGA.
To achieve this goal, we will attach an IP to our parallel to Sariel to parallel design explained previously
in discourse and monitor its signals at runtime.
These are the objectives of this section.
Understanding the concept behind the LRIP customizer LRIP, using the Iola IP to monitor signals in
unnaturalness design.
This section consists of four lectures, this video as the first lecture clarifies the goal of this
section and it's a structure, the next lecture defines the integrated logic analyzer IP and how to
customize that environment.
The third lecture explains how to instantiate annihilate in Rivaldo and connect that to a design and
monitor the runtime signals.
The last lecture, as usual, gives you a couple of exercises to master the techniques explained throughout
this section.
After finishing the section, you will be able to customize and isolate and connect that to a design
in regards to monitor the runtime signals of a running design inside the bases.
Three report.
The next lecture will define the IP and explain how to customize the.
These are our takeaway messages, monitoring the signals inside, and if PJ is a technique to debug
our design at runtime.
Mother provides us with an iron IP that enables runtime debugging.
Now, the quiz question, what is the logic analyzable?