How can we debug our design after programming the FPGA, this lecture will explain how to debug our
design inside an FPGA at runtime.
Monitoring the design port signals on the board is usually the last step of debugging a design.
This monitoring is usually done by using a logic analyzer.
However, physical logic analyzers are usually very expensive and may not be accessible in some situations
to cope with this issue.
We Vado provides an integrated logic analyzer, Ioway IP for this purpose.
The customizable IP core is a logic analyzer core that can be used to monitor the internal signals of
a design.
Dialectal includes many advanced features of modern logic analyzers, including boolean trigger equations
and age transition triggers.
Because the L.A. is synchronous to the design being monitored, all design clock constraints that are
applied to your design are also applied to the components inside dialectal.
Signals in an FPGA design can be connected to these signals attached to the probe, inputs are sampled
and design speed and stored using a chip block from Beera.
The core parameters are specified, the number of probes to sample depth and the width of each probe
input communication with dialectal is conducted using an auto instantiated DeBacker that connects to
the geotag interface of the FPGA.
And I UNICOR has several input and output ports in this course, we only use the basic ones.
Dialla needs a clock to synchronize its functionality and data sampling.
With the design on their test, a set of customizable ports will be connected to design signals under
inspection.
There are other ports which are not our concerns in this course.
L.A. can provide up to one thousand twenty four props.
Each group can have up to four thousand ninety six bits, in addition, each group can be customized
as data trigger or both.
And Iola consists of two main components, a sampling circuit only Bira, the sampling circuit samples,
the signals connected to data and saves them in the bira.
The size of Biram is defined by sample data or depth parameter, representing the maximum number of
samples that can be stored at runtime for each probe in.
Notice that the number of samples is limited by Behram size left for L.A. in an RPG.
We need the mechanism to define the start of sampling the trigger logic circuit provides this triggering
mechanism.
This logic circuit receives a set of inputs through probes that are defined as a trigger type.
These three airports are combined using a boolean expression to generate a trigger signal that feeds
the sampling circuit.
Notice that regular FPGA logic is used to implement the sampling and trigger functionality, therefore
there should be enough resources available on the PGA for both design and.
And the usage has two main steps.
The first that happens during design time and another happens during runtime when the FPGA runs the
application during the design time, if you initialize the IP, customize that and finally connect that
to the design signals.
Customization process includes defining the number of ports Turbit with and also defining the sample
data depth that determines that Behram size.
There are also some advanced features that are not covered in this course.
After the design is loaded into the FPGA, we use the reverse the logic analyzer software to define
the trigger boolean expression.
After the trigger occurs, the sample buffer is filled and uploaded into the device, the logic analyzer.
You can view this data using the waveform bindle.
How can we use an ally in a real design, the next lecture will add an ally to the parallel, to surreal,
to parallel design explained earlier in discourse, and will show the design signal waveforms at runtime.
These are our takeaway messages.
And integrated logic analyzer IP can monitor design signals at runtime and isolate samples of selected
design signals and saves the data in Beera inside the FPGA to be used later for monitoring.
The customization is the first step of using an in a design trigger.
Conditions should be defined at runtime to determine the start of data sampling.
Now, the quiz question, what is the role of the input signal in an era like?