In this lecture, we are going to instantiate an ally in the parallel to surreal, to parallel design
and monitor some of the design signals and runtime while the circuit is running inside the FPGA on the
board.
We customize the aioli to have seven problems.
This table shows the design signals connected to each.
As can be seen, the first on six probes have Apitz and the others have only one bit.
First, open the parallel to Sariel to parallel, if you are the project explained earlier in this course,
it consists of two ities.
The establishment is connected to its light switches and the board and the begin conversion is directly
connected to a push.
But we now know that to connect the push button switch to digital system, we needed the bouncer and
probably a pulse generator IP depending on our design.
So let's modify the design and add those ipis.
You can find the IPS in the resources folder attached to this selection.
Now, at an L.A. EPEAT to the diagram area, in order to use this IP, we have two steps here.
Customize the IP and connect the IP to the design.
First of all, determine the signals that you are going to monitor later at runtime.
We can connect the Ilic input to the design clock.
This clock is used for data sampling.
Let's customize the.
Double click on Dial IP to open the customize IP window.
First of all, choose the native as the monitor type.
Then determine the number of props, which is the number of design signals for monitoring, for example,
seven here.
Then we should configure the probes, go to the probe, underscore reports that.
Here, attached to each port, there are three Parramatta's two of them are important for us in this
cause profit and pop trigger date.
The first problem is going to be connected to the air input, which has eight bits.
The other probes have one bit except Prop five, which has eight bits.
After defining the prop bit with we should define which probes are used for trigger and which ones for
data.
Alternatively, we can keep the defaults in which probes can be used for data and trigger at runtime.
We choose some probes to make the trigger signal.
Now we can make the connections.
Then we should create the ideal rapport and generate down put products and the bitstream.
OK, here we have an another situation, if you go to the message that we can read the error message
as I'm running the Vado on their Windows OS.
It complains about some files and directory paths longer than one hundred and sixty two characters,
if you are using Linux OS, you want see this message.
Just move the project to a directory with the shorter path and generate the with three mega.
Now programmed, bought the device automatically opens the aisles away from window here, we should
define the trigger condition.
And boolean expression can be used to define the trigger condition, click on the icon, then select
the only signal defined as a trigger signal during LRIP customization.
Now we should define the boolean expression here.
The Boolean expression is very simple and we are going to start the monitoring process when the signal
is one.
So the operator is equality and the value is one.
Now we can start the dialogue, we'll start the monitoring process and wait on a high logic value on
the pulse generated by the pressing the push button.
Just press the push button on the board, and after a few seconds, what's this signal wave form in
the L.A. pay phone window?
This is the binary pattern that I have set on the slide switches as the input to the.
As this video is the last lecture in the section that explains the design idea and techniques, the
next lecture will give you a few exercises to practice what you have learned throughout this section.
These are our takeaway messages, dialing IP can be added to our design in Vado for runtime debugging.
The trigger condition is defined at runtime.
If you are using the Windows OS, be aware of the Project Pampling.
Now, the quiz question, what would happen if you accept the default value for Propter, your data
during the Iola customization, notice that the default value is data and trigger.