Welcome to module 8.1 Xilinx I assume Xilinx I assume Xilinx I assume is a tool you can use to simulate
your VHDL designs.
I see them as built into Xilinx IAC tool.
We will be using Altera in order to give you more exposure to both Xilinx and Altera tool sets creating
an AI sim simulation in order to create an awesome simulation.
Cray is Xilinx IAC project as you normally would just be sure to specify that you want to use the sim
simulator as shown on your screen.
Adding a testbench coach project new source VHDL testbench give your testbench a name and then click
next associate design file.
Next you need to associate a design file with this testbench.
Select the VHDL design file you want to test click next.
Then you should see a summary of the testbench you created checks and tags select the testbench and
then click.
Right click on the debt on the checks and tax and then select Run.
If there are errors in the testbench you'll see them show up in the errors tab at the bottom of your
screen.
Insert stimulus.
You will need to modify the testbench in order to place a stimulus on the inputs of your VHDL design
file.
Run your simulation first make sure your test bench is selected then right click on the simulate and
then select Run verify results.
Now you need to verify that the outputs are what you were expecting.
If they're not then you need to modify your VHDL design file and rerun the simulation.
You have just completed module 8.1 I assume.
Here's a summary of the things we went over.
I assume as a VHDL simulation tool that Xilinx provides you can directly integrate your ICM simulation
projects with your IAC design.