So welcome the module 8. to Xilinx ISC project and this module will be learning how to create a file
that will be used to program our bases to board creating a project after you fire up Xilinx IAC.
Go ahead and click on the new project button new project wizard.
This will bring up the new project wizard for the name of your project.
Use the name of the entity of your VHDL design for the location.
Navigate to the directory where your VHDL design is located.
Make sure to select HDL as your top level source type project settings.
The next step in the wizard is disliked all the project settings the base bases to board FPGA as a Spartan
3 device X C S One hundred E and Sep 1 3 2 package with the speed grade of Dash 4.
Select the VHDL synthesis tool and the ice simulator.
We're using the VHDL 93 standard project summary.
Once you have completed the new project wizard the project summary will be shown.
This report will give you all the settings of the project we just created.
Click Finish to create the project add design file.
Your screen should look something like this.
Select the implementation radio button in the View section.
This is where you load our VHDL design file to project at source and this will bring up a dialog box.
Navigate to the VHDL design file you are wanting to load onto the FPGA.
No if you haven't already coded your VHDL file in Notepad post plus or other text editor you can select
the new source and select VHDL file and code the design file in the ISC tool for that two example.
If you don't click on the VHDL file in your project this is what your screen should look like.
Note that the entity of the VHDL file is the same name of the ISC project.
Also no the three squares that indicate your VHDL file is set as the top level.
You can only have one top level VHDL file.
If you have multiple VHDL files in it design the top level would contain component instantiations of
all the other VHDL files.
Map the.
So the next step is to map the FPGA to the IDE to in our VHDL design make sure you have saved any edits
to the VHDL file right click once on the top level VHDL design file to activate it.
Then right click on the IO planning priest synthesis option and select Run.
Note that for all the projects you will be completing.
I'll provide you with the necessary user constraints file.
So you only have to focus on the FPGA development portion.
However if you're wanting to create your own designs this is a great reference for you.
The following two dialog boxes may appear the first dialog box will appear.
If you do not have a user constraints file inside of your project go ahead and click yes.
Xilinx is just informing us that they will be adding a user constraints file or you CEF file to our
project.
This file is used to tell the compiler what FPGA pins are tied to what VHDL entity poor members.
The next dialog box is warning you that you will be editing the same.
You C-f from the IAC project we are currently have open and the new program we are currently opening.
Go ahead and click yes.
Plan ahead.
This will bring up the Xilinx plan ahead tool showing your screen.
The only part we are concerned with is the port section and the upper left hand side.
Note that all the inputs and outputs specified an entity of your VHDL design should show up in this
section.
Here is you showing the entity VHDL design and the Plan ahead screenshot.
Notice that the inputs and outputs of the entity match up with the available inputs and outputs we have
available to map physical FPGA pins to and plan ahead.
This is because the entities section are VHDL design tells us how our design interacts with the outside
world which in this case pins on an FPGA in order to determine what entity ports need to connect to
what pends referred to.
The base is to use your guide where you will find and see your six figure six shows you what pins are
connected to each peripheral for the for example will be using switch 0 1 and 2 for inputs X Y and C
in these peripherals are connected to pins 11 L-3 and K3.
So the output C and S will be using the Ltd's as indicators.
The FPGA pins and M5 and 11 are connected to 0 and 1 which are the LDS.
We will be utilizing.
You should be able to see this reflected in the figure on the right.
Now go ahead and click save and close out of plan ahead.
You if user constraints file when you go back to your ISC project you should see your newly created
U.S. file as shown.
Double click on it and you can pretty easily pick up on the formatting if you want to create new U.S.
files.
You can use any text editor and following the pattern.
Create your own you see files.
However the nice thing about using plan ahead is that it only allows you to pick valid IO pins and you
cannot pick the same pin twice implement in design and generate programming file.
The final step is to implement our design and generate the programming file in order to do this.
Right click on implement design.
Run.
This may take a few minutes to complete.
Then right click on generate programming file run.
This also can take a few minutes after this is completed.
You can look in your projects directory and you should see a B tif file.
This is a file you'll be loading onto the FPGA final report after your program file has been generated
airport giving you all the information regarding to how many Io's you have used.
How much logic your design has used up and an overall summary of your project summary.
We have just completed module eight point two Xilinx ISC project.
Here is a summary of everything we whenever we can use Plan ahead instead of Xilinx ISC to create.
Are you C-f user constraints file.
You import VHDL files into Xilinx IAC or even create them using the integrated VHDL editor Xilinx IAC
is a tool we will be using to generate a program file to load onto our FPGA.