Lab one full adder
full adder and last one we will be implementing a full adder.
I have given you all the necessary files to implement the full adder on your FPGA development board
use module 7.2 as a reference to run the mouse simulation use Majel 8.2 and eight point three as a reference
in order to program the FPGA board.
Good luck Mandelson's simulation.
Here's a screenshot of what your model sim simulation should look like.
Note the transcript in the lower left corner as an indication of the successful simulation tasks.
Here are a list of tasks that you need to do in order to complete lab 1.
Create a model sim project using modules 7.1 as a reference and successfully simulate a full adder create
project and Xilinx ISC using module 8.2 as a reference and successfully create a bat file.
Program your base use to board using module 8.3 as a reference.
Using that file you generated you C-f file pin mapping using the you C-f file.
I have given you.
Here are the locations of all the different entity port members.
You will be toggling inputs y x and in and then verifying you get the correct outputs on C out and s
outcomes.
Here are the outcomes.
Following the completion of LAB 1 you'll learn how to create a Malleson project and simulate a VHDL
design understand how to create a Xilinx ISC project and program in FPGA development board based off
a VHDL design file.
Become more familiar with all Terra's models some simulation software and Xilinx ISC software.