Welcome to the latter but the basis the more I get to go ahead and do a full walkthrough and show you
how to complete the quarter lab and program the basis for the first one to do is open up the Lovano
you'll see what you have already downloaded and we'll go to create new project and this will bring a
little wizard and go ahead and click on next in our project name we want to give it some sort of name
to call it Project.
I'm going to call it water to the.
That's just because they're designed for working with his water too.
And if you put your nose down we have the crate project subdirectory checked.
That's because we want to get inside the folder create a separate folder that contains all of the projects
just makes it easier to maintain and keep track of everything.
So we're headed on next.
And we want to select the RTL project where everything we're doing in this course will be using our
genome project like next.
And this is working at sources here is where you can add your FULL OUTER design file but we're actually
going to do it later on to show you how to add it into the project after it's created.
Make sure our target language is VHDL and our simulator language is mixed which doesn't matter we're
not computing the simulator but just target what you want.
The AGL misses us if we have any IP intellectual property and we go over look next and we don't have
a constrained smile.
We're going to add that after our next.
Now we want to pick that apart.
This is the FPGA that's located on the basis report.
Now if we had certain boards we can suck on board and it gives us three different options there is that
board seven nation platform in the seven direction and we're not using any of those.
So if you are you would select one of these boards but we're using the basis three.
So we're go to parks I mean go ahead and filter through our product category to get all the family want
to select the Arctic 7 and the package is Sep g to 36.
The grade is a dash 1 and that gives us three options here and we have on that basis the board is xes
a 35 T.
The second option that should be on your screen was like that just kind of gives you all of the available
resources.
We have turned 36.
I know that the block RAM 90 the Espies so on and so forth you can just look through it gives you all
the different characteristics of that part.
We go ahead and slide next and it just gives you a summary overview of everything that's will be in
the project go ahead and finish.
And now it's going to go ahead and just give you the whole screen is telling you hey we're creating
the project it's all files you'll need and everything.
And so when you work with us here the vote will set.
That's really nice.
Everything has cost them line of the kind of guy you need how you want to go.
Second notice right away we have your project summary which we don't have any files we don't have we
haven't implemented or synthesize anything.
So there's nothing really to show.
The first thing we want to do is add our design source.
We'll go ahead and write quick well design source and sources at source and we want to go ahead.
It's like the second option add or create a design source.
Next.
We're going to go out and find the water to start the HD file.
So a slight add file and I have it on my desktop but you want to go to the lab one file that you downloaded
then inside of their lab one flatter go to the bases three directory and you should see a four letter
to the HD file.
It'll give you a little trial preview with phenolics like.
And so when you go ahead it's like OK
then and now make sure you have copy source in the project that way if you edit the actual file it will
be inside your actual project so one to make sure you have copy sources and a product check and then
go ahead and select finish.
And you can see we have the full outer to our design source.
So if you double click on it you'll see that it brings up a window that allows you to edit your files
so we're going to make any changes we can do it inside of a video.
So we'll see and next thing I want to do is add a constraint file.
And this is what's going to tell us that this is what maps the port in our flat or to the actual Pendolino.
And this is where we're going to say what are asked and see where what pins are going to be mapped to
go ahead in like the constraints the sources.
Right click and add sources is where want to select the first option and create constraints.
What happens next in order to add files.
And if you go to the same directory where we pulled the latter two types of files select design constraint
files that gives us one option for one or two not accesory we select that that gives you a little preview.
And this is what basically you're telling the design that here's where our production map to go and
it's like OK.
And then we'll make sure you check the copy constraints upon the project finish.
And so right now we have everything we need to go ahead and create this project.
So first up we want to do is that you'll notice on the left hand side of your screen that got the project
manager IP integrator simulation RTL analysis synthesis.
So we want to go ahead and click on the run synthesis button and this is going to go ahead and synthesize
our design and make sure that all the VHDL code we have is understood by the compiler and it is what's
going on.
And if you notice in the top right hand corner of your screen it says running.
Since this is designed we can go ahead and select wall.
And this is just going to kind of go through and explain kind of what's going on and kind of see things
as they happen.
Make sure you got the license for it and it's selecting the Acura FPGA you chose and making sure all
the off you have is with what what is allowed and play upon your computer this can take a little bit
of time or it can go pretty quick which my computer will get older.
So sometimes it's runs a little slower but you'll see it when it had to go and that now it's doing tiny
optimization so it's going to basically go through and look at everything see your constraints file
and everything that we have specified in or forward or to each file and actually map out make sure all
the ports have selected and that there map too and everything is going on.
It also tells you like you're different.
Seek you how much time it's taken to run this.
And it brings up a little message box message box for us to tell those our synthesis is complete and
the next thing we want to do is run implementation and we can do it one of two ways we can like OK here
which is what I want to do.
So it's like OK and now it's going to go ahead and run the implementation and this is where it's actually
going to take and route all of the signals on the actual FPGA.
And if we didn't get a flight cancel or that box didn't come up well up inside you could cook on the
run implementation.
But once you have it running you don't want to click it again.
So you just kind of wait.
And you look in the top right hand corner you can see that it's saying ryme oft underscore design.
And that's just telling you that's running the design figure out how to map everything.
And if your select is on the bottom here it just kind of give you all messages about what it's doing
and everything is happening and when you're not a memory it's using and so on and so forth.
So we just can't wait until this is completed.
If you have any problems in your design if you missed out something we come into the line now this is
where it'll throw a warning or an error telling you that your design is wrong or anything else you've
done something isn't right.
So once you get past the implementation stage we'll go ahead and generate the bitstream which is what
we're actually placed on here.
E.J. so where it is basically is what it has to run.
And when you get more complex designs this can take hours to do.
You have a super complex design.
You may have it may take three or four hours for this to run.
While times will run these overnight an hour is done.
So now we can open them.
Design but we also don't need to open them.
We're just going to go ahead and generate a bit string since we have no errors.
We had a series of warnings that popped up.
So go ahead and look.
OK.
And also that message doesn't pop up.
You can just go to the left hand side of your screen and there's a general bitstream button.
It's great out for me right now because I've already selected it to the pop up menu and you can see
in the top right hand corner that it says running right that street.
It's not actually taking everything and creating the actual file that we're going to load onto the bases
pre-board and with the basic 3-D FPGA we here the bitstream is two megabytes which is what change.
Whatever project you do you always have the same bitstreams size.
And so we have a flatter or we have the 7 segment display.
So have a 2 megabyte stream file.
So it's just running through an OK.
It'll let us know once it's popped up.
Own you can see here in the law it's just kind of telling you what's going on it's creating a map frame
bitstream that's writing it it's giving you the amount of memory use your stream has been completed
successfully.
So now we want to do is open the harbor manager using the reports and see what your resource utilization
is what we'll do after we program more.
Let's go ahead and select the open harbor manager.
This is what we're going to use to actually program the basis for.
So then select OK.
And this is opens up a hardware manager.
Now once when the harbor manager what we want to do is we want to connect freebasing stewpot.
So this point I want to make sure that your basic storyboard is plugged in to your USP and it has to
be in a port and has power over USD which you'll usually denoted by a little lightning bolt next year
years before and you want to make sure your basic support is turned on and you should see the Red Tower
Elodie on just to indicate that you have power on your board.
So you go ahead and under Harbor manager we have this open target.
We want to select that and we want to do things like open new target.
If you've already connected to your bases seaboard you can select recent targets and it should be an
option for starting your day.
But we'll go ahead and open a new target and bring you up to a wizard that will guide you.
We have nothing to our basis or Spanswick next.
And we want to do local server that's because we're at the basis the board is connected to the PC that
we're running here we're actually running on this machine we're not running on a remote server.
Go ahead like next and it's going to go through and check and see what devices it can connect to.
What you should see is that device here is Xilinx thesea digital and it's got a specific code on it.
And if you just leave everything to default this X-C seven eight thirty five t that is the actual FPGA
on the board and it's just saying that it recognizes it's there.
So it's like next wizard.
And then we can go ahead and finish.
And it should.
Now we're connected to the basic 3 board the hardware manager.
And so we want to do is select a program device and it gives us the option of X-C 70 30 40 that's the
FPGA is located on the basis of the board work on that.
And we want to see like a bitstream file and just by nature the default is enough water to project and
create its own directory structure so you can see we have this one or two project that called Dot runs
slash implementation and the water to stop it.
So go ahead and click program and we should see that the LCD base has three board in the top right corner
of the Greenlees is done showing that the basis for the program.
So now our full hour we can test it by going ahead and we have our C out and s are the first two ladies.
So what we notice that is if I push one switch up I've got a binary one out that which tells me that
OK I've got the single input.
So if I get that one down and put another input in I still get a y output that tells me that I have
one switched active.
So out of the three on the right hand side is three switches I can play any combination those up in
the sum of those inputs will be resolved on the ladies in binary format.
So if I put the second one up I have a binary 2 which is a 1 0 up and the third one up or three.
I have a binary 1 1 which is equal to 3.
We're just kind of cool.
I never went out.
I still have a binary to go.
I have to switch up all of the binary to which is a 1 0 5.
Any one of the switches.
Also I have just the finality of one.
Same with the third switch.
And so that is how the water works and that's essentially just kind of a run through of how you would
create a project and bring in your VHDL files and your Excellency files and then go ahead and program
your board and make sure it works.