Hello everyone.
Welcome to the lab one solutions.
In this video I'm going to show you all the steps needed to complete lab one.
So if you're ready let's get started here for lab one.
I have.
There is a zip file you need to download which is right here on my desktop.
And so if you go ahead download that and extract it you'll see here's all the contents inside the lab
one folder.
I've got a folder underscore to a file which is used to the Mollison simulation.
I've got a file which we use in the Xilinx ISC project and this water to it is the VHDL the actual design
file.
So if you right click on that I downloaded notepad plus plus you don't have to use it but just want
to suggest ahead and open that up and you'll see this is the actual VHDL file I provided.
You know notice this is a completed file there is no I don't.
All I'm having to do with this here is just to run through the steps in creating a model sim simulation
in a I.R.S. project.
So there you will have to do any code editing for this lab.
So OK we'll go ahead and normalize out of that now
well I guess we have the lab one tasks which if I open up here gives you a list of all the tasks we
need we need to complete for LAB 1 which are creating models project using the video as a reference
and successfully simulate for our creative project and Xilinx IAC and to create a bit file which is
what we use to program bases to board and then actually use that file to program the Base to board.
OK.
So here.
Go ahead.
No.
So the first step will go ahead and open up our model Semb which if you open it up you should see something
similar to this as your screen here.
And the first step we need to do is change the directory to locate to the lab one folder we set which
is look at our desktop head and all navigate to that
and there it is OK and you have this little transcript down here running kind of telling you everything
that's going on.
So then the next step is we need to create a library for models and then any time you work in model
assume you have to navigate to that directory and create a library to work out of so so a file new library
and makes you select Create a new library in a logical mapping to it and the name Madison gives it his
work and which is fine that's just the default name.
That's the one I always use.
Just go ahead and click OK.
See the transcript telling you that it all is working fine.
So now we want to do is go to Tools.
This TCO execute macro and it brings us to our directory which is in the lab 1.
It shows up you can select D.O. or a DCL file and I've provided you with the TCN file.
Go ahead select that.
This will run through and simulate your pulls in your testbench pulls in the design file and will create
a simulation as you can see here on your screen.
If you go through this is the full simulation and if you noticed down here the transcript window that
gives you a note saying successful water tests completed which is good because I've given you the completed
letter C shouldn't have to do any editing.
And here in this wave window I'll go ahead.
Right click and select on the Zoom for it all matches so it fits your window and you can see if I expand
this here.
It gives you all of the different signals we have in our entity or ASCI out x y S.N. and tell it shows
and toggling your sense or logic tells you there is 0 or 1.
And these are the signals we have in their test inputs and our test outputs.
So that is right there we just completed task 1 which are successful models and simulation.
So go ahead and close out of that.
And the next thing we want to do is open up the ISC project.
Now I'm using twelve point four which if you go to the download you can download fourteen point seven
or any anything later than 2.4 should work.
So go ahead and more click select new project bring up our new project wizard and we want to go ahead
and navigate to the lab one folder that I zip file gave you that you extracted and we'll select that
as our location for our new project.
And as far as the name goes you want to give it the same name as the entity declaration or the VHDL
file I gave you.
And so that is full adder too.
And you see this as a working directory.
This is the location of it.
And for your top level source you want to select HDL your hardware descriptive language and click next.
And here is where you select.
This is all the project settings where you basically specify the device you're targeting.
So far our family is a Spartan 3.
This is the FPGA that's located on the bases to board.
If you're using a different board you'll want to select whichever family of FPGA your board your board
has which it should be.
Tell you in the documentation or user guide and the device is the X.
See 3 x 100.
Which is the one we're using on the basis to board and the ACP 132 pin package speed dash for synthesis
tool will select the X s t and simulator I ice for language VHDL.
Most all these here should be the defaults.
However not just make sure what's on your screen matches what I have going on right here.
You go ahead.
Click next and this will give you a summary of the project you just created gives you all the details
your path working directory top source level a device all that stuff.
Go ahead and click Finish.
And this is your project right now.
It tells you when you got your father to project the device the FPGA we're targeting right here and
there's nothing loaded in here.
This is a completely blank project.
So I want to go ahead and soak in the water to go to project and we're going to select Add at source.
And that's because we've got a source of VHDL file that's already defined.
Now if you're wanting to create a brand new VHDL file you can either a write the code and note external
programs such as Notepad post-process or mulk or model Sam and bring it in like we're doing.
Or you can go to a news source and if you do that you just want to select the VHDL module give it a
file name collect next and it'll add it to your project.
However we're not we are we've already got VHDL files we're using so we get a project at source and
this is when I go back a level to our lab one folder we've got the FLATTR to VHDL file.
I'm actually pick the VHDL file not the use File.
So a slight That looks like open.
OK.
And there we have are four or two is in here.
So if I double click on this it'll bring up your water to the HD.
The VHDL file which is the same file we've seen in our notepad plus plus editors.
Well now if you see these three little three three boxes here and like a triangle type shape thing.
This is telling us a top level.
So for example if I'm going to have a component instantiation and add another HDL file I want to make
sure that there underneath this here which as we go when we have the use file you'll see how that it's
done.
So if I go ahead and I want to make sure that I select on my FLATTR project I'm going to outsource and
this is where I want to select the U.S..
So go ahead and select Open.
OK.
And now it looks like you don't see that you see fall anywhere.
That's because it's underneath this awful lot or two this is our top level this is the ultimate VHDL
file if you will so if you expand on that you'll see it shows this water to your file.
This just shows that this is tied to this for water to design file.
So if I right click on this and I can double click it there and if you double click it you'll see your
UCM file and you can kind of look at the syntax here and get the notation they've got going on.
They've got their next scene which is defining your port member so this next scene is defining this
see important member on the full letter too because an input standard logic and it's pointing into location
PLN and so on the Spartan 3 FPGA pin 11 is associated with this scene and same for Seow same for x x
y which this year you can type in here and edit this or you can you can use the if you click on your
ECF you can edit the constraints to be attacks you can go here you go to your PIN planner which we don't
need to because it doesn't.
You can go this I hope I'm planning right click run.
I'm not going to run through that.
There's If you watch the video and the Xilinx section it goes through on how to do that.
So I've already given you CFA So as of right now this project is complete we just have to synthesize
and create a file.
So in order to do that I go ahead and select my top level.
If I don't I don't select it you'll see there's nothing available for me to do.
As soon as I select it though I've got all these options.
Now I want to go to implement design right click run and you'll see here it's going to run through the
synthesis where it's got to translate it map it place and route.
And this sometimes this is small design that won't take as long but some designs will get pretty big.
This can take three to four minutes or more depending on how big your design is.
So take all that and you might get some morning showing up like I get this warning saying my software
subscription period is lapsed Tavor don't necessarily worry about that mapping place and route.
And you get that green check mark that could just kind of shows that everything is working successfully.
OK.
So I feel like it's working I'm going to go ahead and right click on my generate programming file run
and this is going to run through this is generating a bit stream.
And this is what's actually the doc file we want to load.
OK.
So I went ahead and said that's successful.
So right now this is if we go to our design summary it gives us all the information about this project
tells you all the resources we've used the number of IPOs we've used etc..
So you can see right here we're pretty much just use 1 percent of all all these things here and about
6 percent of the IO.
There's 83 available we use 5.
So that's it's useful information if you're before or even you can create your design and synthesize
it and tell you if you need to step up to get a bigger device or whatever.
So OK so I was right now.
So Step two is completed.
We've implemented our project and we've generated our bit file.
Now we just need to put on the FPGA.
So if we go ahead and bring up a dept we first need to do is make sure your base is to board the jumper
JP 3 you have to make sure that it's selected the PC in order so it can connect to your computer because
if not it's just going to read the information off of the flash chip but just look it on the FPGA.
So once you are selected on PC plug it in your computer turn it on.
Open up a dept and you'll see this and it's going to not identify anything.
Click this initialize chain that recognizes your FPGA and your program will read only memory.
We want to load directly onto the FPGA so we're going to use.
Here we got to select our bit file browse and we've got to go to our desk top of one for our project
and this is the bit file we generated and select Open and you'll get a warning about the clock.
However you don't necessarily to worry about that.
Go ahead and click yes click the program and give you no warnings.
Go ahead and click yes.
You'll see the video on your base two word flash.
And as you can see down here it tells you that programming was successful and once you did that we've
completed step three and once we get to this point you have successfully completed lab one.
And now if you're ready go ahead and move on to the lab to.