WEBVTT 00:00.840 --> 00:08.680 Welcomed a lab to the shift register shift register and map to. 00:08.740 --> 00:11.710 We will be creating a shift register. 00:11.710 --> 00:19.480 There are many types of shift registers parallel and parallel out Universal shift register serial and 00:19.600 --> 00:28.180 serial out serial in parallel and many others shift registers are a very integral part of any digital 00:28.180 --> 00:29.540 logic circuit. 00:29.590 --> 00:38.170 We will be creating a serial and serial out shift register in this lab model simulation. 00:38.370 --> 00:42.940 Here's a screenshot of what your model sim simulation should look like. 00:42.940 --> 00:48.180 Note that there is no transcript output telling you that your simulation worked. 00:48.200 --> 00:52.220 There you can look at the wave form and see how the values are stepping down. 00:52.240 --> 01:00.580 Every clock cycle this is showing how big it is shifted through the register tasks complete the following 01:00.580 --> 01:01.360 tasks. 01:01.360 --> 01:10.900 For lab number to complete the shift edge VHDL design file I have given you successfully simulate your 01:10.900 --> 01:19.620 VHDL design using models and use modules 7.1 as a reference implement the completed shift register onto 01:19.630 --> 01:25.990 your bases to board using modules 8.2 8.3 as references. 01:26.920 --> 01:31.060 You C-f pin mapping using the use File. 01:31.060 --> 01:32.420 I have given you. 01:32.530 --> 01:36.760 Here are the locations of all the different entity port members. 01:36.760 --> 01:42.170 Feel free to modify the USCF file if you want to change the locations of things. 01:42.250 --> 01:46.680 I suggest you try and shift the outputs to left by for Ltds. 01:46.720 --> 01:51.510 This would be great practice and learning how to modify a U.S.A file. 01:52.240 --> 01:56.680 Here's a list of the outcomes upon the completion of lab to you. 01:56.680 --> 02:04.510 Again experience in coding VHDL you understand how a shift register works and is implemented in a VHDL 02:04.510 --> 02:05.530 design. 02:05.530 --> 02:09.220 Become more familiar with interpreting Madison simulations. 02:09.790 --> 02:16.750 Become more familiar with Xilinx IAC as a tool for creating programming files from a VHDL design.