Lab three universal shift register universal shift register a universal shift register as a shift register.
That can shift data to the left or the right.
We will be using a serial code universal shift register.
Here is the tasking for lab 3.
Use the VHDL design file.
I have provided and complete the universal shift register design simulate the universal shift register
and mouse and using the supplied testbench and TACL file.
After you have successfully simulated the universal shift register create an IAC project using your
completed design in the U.S. file.
I have provided model some simulation.
Here is the model some simulation of the universal shift register.
If the waveform looks intimidating to interpret Don't worry.
The transcript output will tell you if your simulation was successful.
You see if pin mapping using use file I have given to you.
Here are the locations of all the different entity port members.
Note that you will have to manually toggle the clock.
Also if you want to reset your universal shift register be sure that you're holding the reset button
down while you reset the clock but outcomes here are the outcomes upon completion of lab 3.
You'll become more familiar with models in understanding how valuable it is to test your VHDL design
become more familiar with Xilinx IAC tool.
Understand how a shift register is implemented in VHDL and how you could create your own variations.