Go Welcome to the fab three solutions video in this video one will walk you through the steps needed
to complete lab 3.
So in the lab 3 section there is a zip file lab three which you go ahead and download and unzip which
I've done here on a desktop.
Then when you zip that there you will see there are there is a folder called tests a score bench on
a score Ellaby.
This is contains a home a library package it'll be used in your test bench.
Don't worry about it.
However make sure you don't delete it otherwise your testbench will simulate.
So just leave that folder go in and make sure you keep the structure the same that's very important.
As far as the DCL script I give you know we've got this U.S. Our folder which if you go and open that
up that's what contains your VH DL file.
The US are the HD filer here and TACL script your test bench your test us are an input output which
are CXXVI files.
These were your testbench uses and you get your lab 3 tasks which will open up here.
And as you can see we've got four different tasks here for lap three tasks one is to complete the U.S.
HD file by filling in question marks and then we want to create a Mollison project using module 7.1
as a reference to successfully simulate your just your design.
Then after we successfully simulate it model Sam will want to create a project in Xilinx C and to create
a file that will use that file to load onto the FPGA and verify that everything's working as expected.
All right.
So for the first task is to simulate or fix essentially the the US or file the VHDL file.
So what I want to do is go ahead and.
OK I'll go into this us our folder here in your lab three directory and go ahead and open that up I'm
going to do these edits with notepad plus plus.
You can do them with any editor really you could even use just regular notepad.
However I like Notepad plus plus because you can select your language to VHDL and there it picks up
on that and explain syntax and gives you a different color so you can kind of note between keywords
and comments and everything else.
So here's our US our VHDL file.
So I'll give you the task by label and here in the file and some comments and then go to our libraries
or entity.
And if you go through you'll see I've got this a sequel to this question mark.
Well these are basically you've got to go through and figure out what these are.
So first thing to do is we're going to go ahead and open up models because this is typically the the
process I'll go through in order to solve this.
So we open up model Sam we've got to file new.
Are we going to file change directory and we want to navigate to that U.S. our directory which is in
the fab 3 folder us our.
I click OK and yes see your transcript window kind of telling you what's going on and to file new library
because anytime you create a change your directory in your work with models you have to have a library.
This is where it stores the simulations and everything.
You only have to do this once if you open this directory up later on.
And it's you still have the library called work which I'll show you here once.
So you just want to select a new library and a logical mapping to it.
And the default is work which is fine that's just what I leave my house.
Go ahead click OK.
And if we open up go to this directory here you'll see we've got this lab three US are.
We've got this Madison configuration settings file and it creates this work folder which we go into
there.
There's just that's where when we simulate it's going to store all that data in there.
So that's all that's really doing.
All right.
So now we're going to go ahead and we're going to attempt to simulate this.
So I'll go to my tools TCO execute macro and you want to select that you start PCL file that is included
in your lab lab 3 former structures.
Go ahead and select that and it's going to tell you which this is where you get the transcript down
here.
It's saying it's got some errors.
And this is where it's telling you and then your USRA HD file line 47 and there is a syntax error.
And so if you go into here line 47 had picked it up.
It does not recognize what that question mark is and because questionmark is not is not defined basically
so.
And that's why I did that.
They are designed to make you go through and hopefully figure all this out.
So ok for this line 47 it's telling us we need to sign the output to what.
Well if you look here.
We're going to sign that to a wretch because we can't read what the value of a is.
And so we're going to have this signal a ridge that we modify and associate it with this output.
So to solve that we'll go ahead and type in the range and as you'll see it will pull up a little box
saying all they read is that what you want to use and yes we do hit enter and so no that that should
be fixed so let's go ahead and go to the transfer window a model sim right click clear.
That clears it out and we'll go Hago tools DCL execute macro while we execute it and see we still got
more errors.
But exactly that was a problem I didn't save it.
So you had to go through here and it still picked up on the error on line 47 because we didn't say this
so it hit save.
We'll go for it I get it real quick I'll clear that.
Go to Tools to C-L execute macro or us are TCO.
And now it's saying we've got an error on line 53 and got 69 75.
However typically this isn't all the errors like Usually after picks up one or two errors it'll just
exit because at that point it doesn't know what's going on so you open this up and we'll go to line
53 that's for the next areas right here.
It doesn't recognize that questionmark again.
So we've got to go through this.
And so far I hear basically this is a VHDL process and we want this to be evaluated on every clock cycle.
So what do we need to put insensitively less we need to put the clock signal and the sensitivity list
which appear in our entity declaration is our clock has to find us.
OK.
So if I go ahead and put C OK in there and then I want to save and I'll run through this one more time.
Clear your transcript models then go to Tools TCO execute macro select the TC file again open and now
it's telling us on line 58 and basically outhe's continue this process until eventually a model some
will go ahead or compile everything when all of the errors are gone.
All these question marks in and you see a note saying that you successfully simulated the US are so
we're going to go ahead and just go through I just did the first C like that just to kind of create
the process I usually go through.
So as we go down here to line 58 we're in a reset process so on every clock edge we're checking to see
if the reset is one or if it's being pressed and if it is being pressed we want to set a red edge to
zero because every edge is tied to AA which is our output.
So if I go ahead I'll just put a zero in there.
That should fix that air will save more to keep on moving down and then we'll attempt to see if we if
we got this right.
So now this case statement is evaluating the signal s which appear on our input.
Here is a standard logic vector one down at zero.
That's two bits and representative.
If it's a 0 0 with both bits are low we want to hold.
Well for one to whole we want every edge to be a red again.
So where just put a edge there that hopefully should solve that air.
Now we have this whole right shift process.
This is where we got to 0 1.
We want to shift everything to the right and so we're shifting everything to the right.
If you think about it the the far left most bit is going to be the state or with which we have set as
a minus one which is a 7 a ridge on a 7 is the MSP most significant bit.
We want that to be zero.
Because you are shifting over we're basically filling in zeros.
So in order to make that zero 0 0 there.
Now note I have to put if I follow up I would just leave this like that as a zero.
This would give me an error which I'll go ahead and show you here.
We'll save here.
Clear tools.
Just yell execute macro.
Us are open that up and line 66 is tell us we got there and that's right here.
That's because I need to put those apostrophes on your side of it as you can see here down on line 73.
There's.
I've got those apostrophes on it.
And that's because the standard logic vector.
If this was an integer that would be OK.
So I've got to put these different apostrophes in there and that.
Now that should except that if I clear tools to execute macro
and that's and that's the process this is a process I want you to use and you go through here.
So now it's time we've got to err on line 69 which we know because we haven't figured this out.
So now we need to determine OK we're in the right shift process so we went and we took our leftmost
bit made that a zero.
Now we need to make the rest of them equal to what the previous ones were before and basically just
shifted over and essentially you can just use his left shift process as a as a reference.
So over here we're going to want to make this equal to a ridge or dedo.
That's our generic minus one down to one and then therefore basically we're taking all this data with
two here and we're doing our right shift with it.
So save that and then we've got on this line 75 here a serial load.
OK.
So you want to load.
This is where we load values in.
So we're going to loaded it on a registry and we determine what what value do we want to load in.
Well what's our input entity value our input into the value.
Is this I instead logic school for make that and I go ahead and save now see let's try and simulate
this.
OK.
Tools you know execute macro.
Open that up and OK everything compiled successfully and voila.
You see we get this note.
No success us our test completed.
So I'll go ahead right click zoom fool.
You can see all all the way form everything that's going on here which is a little bit difficult to
read.
You can sit here and go through all these toggling a clock cycles and making sure that all your bits
are shifting as as expected.
But when you get the more complex designs this really is not not what you want to be doing.
So typically it does have as you get more advanced you'll learn how to write test benches and inside
a test bench if everything works as expected you'll get this note saying success.
And usually in design process you have a separate engineer who will create the test bench.
That's compared to you and then that way if if his test bench successfully completes your design then
you say that your design is verified and ready to go.
So all right.
So we've got that we've got the first two steps completed.
We went ahead and we completed the lab we successfully all the question marks in our code.
We went through and got it to compile successfully and we were able to successfully simulate and model
them.
And that's usually the flow you're going to want to use with all the rest of.
Right here you're going to probably end up.
And that's why I give you this DCL scripts you're going to be having an editor like Notepad or whatever
you're using to edit these files and you're going to edit them save your tools TCO.
Run a macro run the macro script and just keep reading the transcript they're just going to tell you
the line where your errors are at and just keep following that until you get to successfully simulate
this.
So all right our next step is we want to go ahead and create a project in ISC.
So go ahead.
All right so now that we've completed our model sim simulation we want to go ahead and create our Xilinx
science project.
So go ahead and bring up the IAC and you'll see the screen here.
We're going to go ahead and click on the new project and we want to go ahead and navigate to another
location.
Navigate to our lab three and click on the US are opened up and then give with the name we just want
to want to make it.
USRA because that's the same name as the entity which is just good practice to do so.
Click next and you want to select all the project settings that are tied to the FPGA you're targeting
which were targeting a Spartan 3 on the basis to board which is the device ex-chief 3 x 100 the package
C.P. 1 3 2 SPI dash 4.
If you're using any other type of development board you'll find all this information located in the
User Guide or even if you look at the board itself.
The FPGA chapel typically have to have a part number on there you can look that up online and figure
all this information for here.
Most of the stuff once you select these first five different values the rest is here you can pretty
much leave as as our state are so good.
Next gives your project summary finish.
And here we've got an empty project.
The US are going to go ahead and select the project add source and got to go back one level to find
this US R-FL.
Now since we went ahead and successfully simulated this a model said there should be no problems with
this workings.
Why not go ahead and add the source file.
If I double click it give me.
You'll note it should have picked up all the different as you can see we've got a ridge there picked
up all the different changes we made on it there.
So if we had not made those changes and mouse them and we try to synthesize this it would give you errors
and you could debug down here.
However you could have it wouldn't stick.
It might not necessarily work well it's going to do is tell you this.
Syntactically it's correct.
It just it may not be doing what you want it to do.
Like we could tie this a two we can make it it had a second signal one here and tie it to that and change
it or.
The biggest problem would be in this right shift left shift.
We could mess that up.
We could say OK instead of data register with minus one and make it data register with minus 2 and so
on and so forth then we could have something that works be thrown on the board it doesn't do what you
want.
So OK so now we need to add the U.S. file to a project source and then all us our.
So here you go up to the lab three the top level you've got that this U.S. file.
I want to go ahead and select Open on that.
OK.
And now you expand this down and you want to make sure that your the HD files are top level which has
this three triangle type of thing going on with double click or you see efile you can see we've got
now in our beach do you we've got a which is a standard logic vector data with one minus one down to
zero in our data with a.
So it's a standard logic vector 7 down to zero which if we go all you use in order to associate each
one of those values we've got a zero through a seven.
So we're tying a zero to location 5 which like in the User Guide and 5 is a good output to an LCD on
the basics to board.
And all right so now we've got all the files we need in here.
So we got to select our U.S. our behavior VHDL file.
You'll notice if I select this us our ECF file it doesn't give you options to generate a bit file because
you can't generate it with just that you need a VHDL file.
So we select that and it gives us all these options down here we can do.
So we want to go to implement design right click run and I'll tell you it's running self-assess it's
going through and synthesizing and checking and syntactically making sure that everything is correct
which if you got to simulate correctly in Madison this should be working no problem.
You may get a few warnings telling you that your software subscription period has lapsed.
However if you just recently download the probably won't see this warning.
I've I've had the software on my computer for several years so that's why it's giving me a warning but
it's nothing nothing major If you see that don't worry about it.
Then the next thing one is generates the programming file.
Go ahead and click run.
And this is going to create our top file which is the actual file We're going to load onto the FPGA.
So once you create and that's a staggering check saying that that's that's good.
Once you create this file you can literally take this file anywhere.
You can e-mail it to someone and they can load onto their FPGA because that contains everything it ties
in this VHDL file.
This design turns it all into the logic gates that it synthesizes to and this file and ties all these
inputs and outputs to physical pins located on the FPGA.
And that's that's that's the thing we want we want that program file.
So that's generated.
We can go ahead and minimize that number want to open up a dept before you do that.
Make sure that on your bases to board your jumper 3 is there is PC and Rom make your on PC.
This does you need this to be connected otherwise your computer won't recognize the board and you will
bear load any files on it.
So make sure selected the PC power on and plug it into your computer.
Open up it dept and you should see something similar to this now.
Right now it says no device is identified.
So go ahead and click initialized chain and you'll see it runs a scan and picks up the FPGA and programmable
Read-Only memory located on the board.
So I go ahead and browse and I want to browse to my one of my desktop lab three folder and the US are
indoor basically the project directory for the IAC so we can navigate to this U.S. Arbet file which
is what we want to get open that up and you might get a warning on here something about the clock don't
that's OK.
Yes.
And then you want to hit this program button and you might get another warning if you do it.
Yes.
And you'll see the status Elodie on your basis to ward flash back and forth.
But you know that it's programming and you'll get a note down here saying preparing to program programming
and programming successfully so it looks like it's successfully simulated.
So at this point you should be able to view the demo video and basically implement the same functionality
that I was doing on there.
And now at this point you've successfully completed lab 3 so go ahead get ready and start lab for.