Welcome to Lab 5 counter
Moulson simulation here is the model some output of the counter.
If you change the rate x to unsigned it is easier to read refer to all Taro's tools section Mollison
video.
If you're unsure how to do this.
Here are the tasks for Lab 5.
Modify counter 1.
VHDL file to create a counter that counts from 0 to 255.
I suggest implementing processes to achieve this successfully simulate this design and model some into
what this design on your base is to board.
You see if pin mapping using the U.S.A file I have given you here the locations of all the different
entity port members you should see a counter accounts from 0 to 255 and binary on the Ltds when you
press the reset button which is button zero.
You should see the count start back at 0.
Here are the outcomes.
Upon completion of Lab 5 you should understand the use of the generate statement.
Learn how to design and develop processes in your VHDL design.
Understand how useful counters are and what they can be used for.