Welcome to lab 6 the multiplier
multiplication in FPGA is FPGA is by nature are not designed to implement multiplication.
However most FPGA today have embedded dedicated multipliers.
The Spartan 3 which is the FPGA we are using contains only four dedicated multipliers.
So if all these are being used by different process we would have to implement one of our own binary
multiplication in order to implement our multiplier.
We will be simulating binary multiplication of two numbers.
Here is an example of binary 12 in binary 13 multiplied which produces the same result as a decimal
equivalent.
This process just takes more time to complete multiplier state machine.
We will be implementing a state machine to determine when we are shifting adding and when the multiplication
is done.
Take note of the names of the different state machines and the signal names.
When you look at the VHDL design file multipliers state diagram.
Here is a block diagram solution to the multiplier design lab.
Note the name values when you're looking at the multiplier.
VHDL design file multiplier operation.
Here's a table to give you a much more clear understanding of what is going on inside the multiplier.
We will be creating a force multiplier so that way we can implement this design on the basis to board.
However this design can be scaled up or down to whatever size you would like.
Mollison simulation.
Here's a screenshot showing the multiplier simulation.
Here are the tasks for lab 6.
Complete the molt 1 HD design utilizing the state machine simulate your completed design and model asem
implement your completed design using Xilinx IAC and run it on your bases to board.
No you will have to modify the file using the U.S.A file.
I have given to you here the locations of the different entity port members.
Feel free to modify the VHDL code see if you can display the result on the 7 segment displays by instantiating
the hex to 7 seg component using lab 4 as an example.
Upon the completion of lab 6 Here are the outcomes.
You understand how a state machine can be used and implemented become more comfortable with FPGA prototyping
understand how to add a user constraints file on an FPGA.