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Welcome to variable's signals files and Constance the deal in this lecture I'll explain how variables

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signal's files and constants are use and HDL designs.

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First we have this term called data classes as in any other programming language.

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VHDL contains different data types and also to further you have a data type and you have a data class

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to each data type specified by data class and in VHDL there are four different data classes which we

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have signals constants variables and files.

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Signals are an object with the current value and projected values and the projected values can be changed

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as many times as possible.

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These are one of the most common class you'll use in your designs.

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These are if you think of signal there what's inside of your FPGA or CPB or whatever you're trying to

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write in your VHDL design and we use the signals to construct construct internal buses shift registers

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Ramm or almost any other type of digital circuit we create.

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We are going to create signals.

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Variables are an object only with a current value variable values can be changed as many times as desired.

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And they go away after synthesis these typical when we have a variable we use it inside of a process

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if we want to perform something sequentially.

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But the most common thing we use them for are the construction of Gates components or other pieces of

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digital hardware.

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When we actually are creating our design we're mostly going to use signals what we will do is use variables

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to help route and construct the signals and constants.

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These are objects whose value cannot be changed after it is initially specified.

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These are most valuable when you have a large design and if you have something say a clock speed you

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can define a constant and call it clock speed and give it a value.

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And if you use it like 10 or 12 or hundreds of other times in your design instead of going through if

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you want to change your clock speed having to change a hundred lines of VHDL code you can just change

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that constant one time and it'll propagate through your entire design.

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So for example we have a constant we would give it the constant which is our data class clock count

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an integer and we give initial value of 50.

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Now once we call our count and it's a value of 50 we can never change it.

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It will be 50 throughout the entire design if I try to assign another value to count.

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I would be an error and tell me you can't do that count as 50.

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It can never be changed.

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We can also use constants to define constants later on.

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So for example we have a constant where coin clock freak for for frequency.

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And it's an integer value.

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Then we have a second constant we call it Max clock count and it's another integer value that we're

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saying the max clock count is equal to clock frequency divided by baud which are baud as another constant

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we had to find.

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So this is where you can have all these constant set up where you just change one value such as your

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clock frequency and you automatically calculate your Bodd your max clock count or other constants along

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the way.

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And so conses are very useful in your VHDL designs.

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Files these are an object that consist of a sequence of values which we have text files or cxxviii files

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in a Synthes sizable design.

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We won't actually use files.

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The only way you may use these argument initialize like memory values inside your design but most commonly

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with a file class is only for test benches for simulation.

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You can actually read values in from the files and take these values to apply to your stimulus.

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Now you're familiar with all the data classes.

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Next we're going to learn about the different data types.