Welcome to variable's signals files and Constance the deal in this lecture I'll explain how variables
signal's files and constants are use and HDL designs.
First we have this term called data classes as in any other programming language.
VHDL contains different data types and also to further you have a data type and you have a data class
to each data type specified by data class and in VHDL there are four different data classes which we
have signals constants variables and files.
Signals are an object with the current value and projected values and the projected values can be changed
as many times as possible.
These are one of the most common class you'll use in your designs.
These are if you think of signal there what's inside of your FPGA or CPB or whatever you're trying to
write in your VHDL design and we use the signals to construct construct internal buses shift registers
Ramm or almost any other type of digital circuit we create.
We are going to create signals.
Variables are an object only with a current value variable values can be changed as many times as desired.
And they go away after synthesis these typical when we have a variable we use it inside of a process
if we want to perform something sequentially.
But the most common thing we use them for are the construction of Gates components or other pieces of
digital hardware.
When we actually are creating our design we're mostly going to use signals what we will do is use variables
to help route and construct the signals and constants.
These are objects whose value cannot be changed after it is initially specified.
These are most valuable when you have a large design and if you have something say a clock speed you
can define a constant and call it clock speed and give it a value.
And if you use it like 10 or 12 or hundreds of other times in your design instead of going through if
you want to change your clock speed having to change a hundred lines of VHDL code you can just change
that constant one time and it'll propagate through your entire design.
So for example we have a constant we would give it the constant which is our data class clock count
an integer and we give initial value of 50.
Now once we call our count and it's a value of 50 we can never change it.
It will be 50 throughout the entire design if I try to assign another value to count.
I would be an error and tell me you can't do that count as 50.
It can never be changed.
We can also use constants to define constants later on.
So for example we have a constant where coin clock freak for for frequency.
And it's an integer value.
Then we have a second constant we call it Max clock count and it's another integer value that we're
saying the max clock count is equal to clock frequency divided by baud which are baud as another constant
we had to find.
So this is where you can have all these constant set up where you just change one value such as your
clock frequency and you automatically calculate your Bodd your max clock count or other constants along
the way.
And so conses are very useful in your VHDL designs.
Files these are an object that consist of a sequence of values which we have text files or cxxviii files
in a Synthes sizable design.
We won't actually use files.
The only way you may use these argument initialize like memory values inside your design but most commonly
with a file class is only for test benches for simulation.
You can actually read values in from the files and take these values to apply to your stimulus.
Now you're familiar with all the data classes.
Next we're going to learn about the different data types.