Look at the standard logic factors standard logic data types lecture in this lecture I'm going to explain
to the HDL data types standard logics and standard logic vectors standard logic data types are defined
and package standard logic 1 1 6 4 stair logic type is either a 1 or a zero.
At this level is based upon the voltage level supplied to the FPGA.
So to us we say sound or logic is a 1 or 0.
But inside that APJ for parent with a three point three a logic one is a three point three ball and
the logic 0 would be a zero goal or for powering it with 2.5 volts logic one will be 2.5 volts and zero
would be zero.
It's a standard logic to type as a single binary bit.
And this is denoted by the keyword as Tity underscore L-O GC or standard logic.
Let's take a look at a standard logic Stehr loving datatypes are commonly used as flags or indicators
that either tell you a yes or no you're good to go you're not a lot of times these and to indicate a
delay has been reached.
A button has been pushed or other things of this nature.
So if we have let's look at how do we do you know a standard logic we have or data class which is a
signal or signal name which we're calling P.W. and underscore value in our data type we're specifying
as a standard logic and we're giving it an initial value of zero.
The only other option we can give it as a one if we try to put two zeros or two ones in their synthesizer
is going to throw out an error at a time.
This is an invalid error.
I don't know what it can be either can be a one or a zero.
Standard logic vector data types they are also defined in a package standard logic one 1:06 for a standard
logic factor is a set of multiple standard logic values.
So if you think of the name standard logic factor it's a vector of standard logics.
So your standard logic is a single bit a standard logic vector is multiple bits and the wit or the number
of bits you specify when you denote the standard logic vector.
So with a a vector you can be any combinations of ones and zeros.
If you have to let's say it's a two bit wit you can have it 0 0 1 0 1 1 or any any combination between
you can come up with a standard logic vector as denoted by as to the underscore EHLO g i c underscore
vector or standard logic vector an example.
We use standard logic vector datatypes are commonly used to hold address's data Ltd. to light up LCD.
You can use it to send data to a 7st display or a lot of different things.
This is a very commonly used data type in the HDL and the main advantage is that you can individually
toggle bits.
So if you have for example a simple example a whole array of Ltds you can create a standard logic vector
to a whit if you have 15 trollies.
You make it 15 bits wide and you can individually toggle each bit to either turn that Elodie on or turn
that Elodie off.
So if we have an example of how do we create a center logic vector we have our data class which is a
signal we have our single name we're calling seg out in our data type is the standard logic vector and
then we specify the size of that standard logic factor.
In this case we're specifying it to be 7 bits wide from 6 down to zero.
That gives us a total of seven bits.
And then our initial value is the actual value of those bits.
So we have 1 0 1 0 0 0 and with that initial value that can be any combination of ones and zeros.
We want to come up with.
And that is a standard logic and Sandu logic data vectors lecture.