Well sign the initial values in VHDL.
Are a few examples we can look at to show you how that is done.
So first for line number one.
Just a quick comment to showing you that in your dash dash your comment and your work you know notepad
plus plus as you put the dash dash there you'll notice that your text or anything and type turns green.
So it's pretty neat that when you type a key word and no Paphos Plus how is it what you know that it
recognizes that it's a VHDL file.
So we go ahead and type a type signal in here which is a key word and VHDL and you see this is this.
As soon as I start to type it it shows up there in the dropdown I go and hit enter and then it turns
blue and Kate knows that that's a signal.
And so is the quick way to bet if you're using the Apply Plus plus a key thing to remember if you're
editing a file in Notepad plus plus when you if you go to a file you go ahead and create a new file
and it's going to right away.
It is called a normal text file.
Want to click on language go down to be like VHDL.
Now it will call it the age as I see Hurlburt a script of mine which file.
So now if I type it will pick up signal because I know that that's the key word enter.
It makes it blude indicate that that's a key word.
I'm not going to keep this almanacks of that.
So I will go to our back to our example here.
And so first I have signal A which is a type of integer and I want to give an initial value of 4.
So I have my signal a then I have to do a semi-colon there to a colon to indicate that my data type
which is in the keyword which you notice is is purple.
And then I'll give it a colon equals four.
So what this is doing is I'm saying I have a signal I'm calling it a.
It has an integer type integer an initial value of.
If we move down to three on line with a mindset and we have signal B and.
And do you mean this is a type unsigned with an initial value of 0 0 0 0 because we work with unsigned
and signed.
We have to give it the actual bit values because an integer we can't give it like a 1 or 0 or so on
and so forth.
And so if you look I have signal B my colon indicates the data type unsigned and I give you the keywords
3 down to zero which just means I have an unsigned data type of 4 bits and if you look then I have a
colon equals which I'm going to have the double parentheses which just indicates all the bits.
So it's giving an actually signal B is four bits.
All of them are initialized to zero and B one if you look on line 10 is doing the exact same thing except
we're using the other's key word message to show you you initialize with larger values that you can
see that instead of if I would have liked this is only forbit.
So it's not as big of an issue.
But if this were to be I don't know like a 12 or 24 32 ribbon 64 bit signal instead of putting in 64
zeros in my file.
I can just have this other.
And the zeros there and that keyword will actually initialize a signal be 4 bits wide all with zero.
And if you look down on lines 18 21 with my signal C and C 1 we're doing the exact same thing except
that we're working with these are actually signed values which I have as unsigned because OK I can just
go ahead and read that down to see one on line 21 and move on.
So now signal C and C 1 are doing the same thing as signal B and B one except there sign two types as
opposed unsigned.
And we initialize them in the same way we use the colon equals and give it the value y initialize it
to move down.
Let's look at signing initial values to standard logic sectors.
So we have a signal looking on line 31 we wanted to fine signal a signal and name a as a standard logic
vector data type with an initial value of all ones and count them not there but there's eight ones.
So what we'll do.
We want to put the key signal and type a and have a colon then put the data type which is a standard
logic vector with underscores between the standard logic and the logic and vector and then have 7 down
to zero which indicates that we have 8 bits from 7 0 and colon equals the others.
It was arrow and put one in parentheses.
Well that's going to do is give us a signal a bit hyped and logic vector 8 bits wide and all the values
will be equal to 1 and we're doing the same with the signal we're going to call red saw the score range.
Now we have a red edge and we want to give the initial value of 0.
So we're going to have to signal signal a signal a red a red is going to be the same exact size same
data type standard logic vector over a red nose.
It has a 1.
We want to make it initial value of all zeroes.
So I have to do is on the one backspace Weiss's zero in there.
So now we have signal a of 8 bits all ones signal A-rag that's all zeros.
And made a little note in here just to kind of show you this is correct.
So I wanted to take.
They make it equal to a red edge and or that I just type the arrow equals.
So and this is a concurrent statement.
So always were were saying that our signal a red edge is being kept the same way.
A lot of times you'll do this when you have to not have two signals but when you have a signal but it's
like of a with an output on the port map it has a red edge.
So you can write values into this registry.
And then the map too.
So if you know after this point of her 1:42 our signal is equal to all zeros and way red equals it's
quick little example showing you how to initialize values and HGL and give them some meaning.