WEBVTT 00:14.730 --> 00:22.350 Here's the behavioral for after you know slicking line one you'll notice a comment the two dashes and 00:22.350 --> 00:26.460 then you look at the text afterwards. 00:26.670 --> 00:30.220 It isn't brain which is indicated that it's a comment. 00:30.270 --> 00:37.080 So we moved down to the next line line 2 and 3 2 is we're saying that we're going to use the library 00:37.090 --> 00:46.250 the Tripoli library and then line 3 is telling us to use a standard logic 1 1 6 for all. 00:46.440 --> 00:52.890 So what that tells us is that allows us to use the data type standard logic and standard logic vector 00:54.000 --> 00:59.750 Rebello that you can see if we have an entity which is called for water too. 00:59.880 --> 01:07.440 And if you'll notice on line 14 the behavior named the architecture behavior and the of the word tells 01:07.440 --> 01:09.150 us that water too. 01:09.420 --> 01:15.060 And you can notice the different keywords in VHDL when you're using Notepad plus plus the keywords are 01:15.060 --> 01:23.430 highlighted in blue or green or yellow gray that just highlight different keywords to different colors. 01:23.430 --> 01:30.180 And we look at our outputs we have S and see out which are the data types and logic just meaning that 01:30.440 --> 01:34.220 there they're either a 1 or zero and it only a single bit. 01:34.480 --> 01:44.670 If you look at the inputs X Y and C and we notice that there a one bit standard logic as well that we 01:44.670 --> 01:53.700 have on line 16 and 17 the out there signals which just means that they're internal to our FPGA they 01:53.700 --> 02:00.450 don't actually get mapped to anything on the board and we call them inputs and outputs. 02:00.450 --> 02:06.960 Now if you notice the signal inputs has is a standard logic factor which mean two down to zero which 02:06.960 --> 02:08.530 gives us three bits. 02:08.640 --> 02:10.970 And if you notice we have three inputs on a report. 02:10.980 --> 02:17.460 So essentially what we're doing is we're mapping our inputs to the three inputs we have. 02:17.700 --> 02:25.640 We're taking every inputs x y c underscore n and we're mapping them or input our signal inputs and we'll 02:25.650 --> 02:26.770 do the same thing with the outputs. 02:26.760 --> 02:33.630 We're just going to generate the outputs and then we map the output signal to the signals declared and 02:33.630 --> 02:38.310 write to you and then we have the keyword begin to move down. 02:38.310 --> 02:44.220 We have another comment the dash dash creates another comment comments so if I start typing here someone 02:44.370 --> 02:53.490 put dash dash and all of sudden it turns green because it indicates he knows that that is a comment. 02:53.740 --> 03:06.520 So here we have our inputs with arrow equals what we're doing is taking the inputs see an X and Y and 03:06.520 --> 03:10.840 concatenating them together which is indicated with the single ampersand. 03:10.870 --> 03:16.960 So we're taking our why ampersand and with our X ampersand and with RCN which concatenates all three 03:16.960 --> 03:23.630 of those which are each a single standard logic value two inputs which is indicated as a standard logic 03:23.620 --> 03:25.850 factor two down to zero. 03:25.930 --> 03:31.460 And so this math adds up and it'll work out OK in our C hours. 03:31.720 --> 03:34.180 We could do it for our outputs. 03:34.210 --> 03:37.380 We could do a ampersand to concatenate them. 03:37.390 --> 03:43.000 This is just showing you a different way of doing that by using the parentheses to indicate that the 03:43.000 --> 03:50.820 outputs are one which would be our most significant bit is being mapped to our Out in our output zero 03:50.830 --> 03:59.800 which is our least and if it can get that being added to our pasts and here we have a process named 03:59.830 --> 04:05.510 after process and that there's another keyword. 04:05.530 --> 04:10.030 The process keyword we have are inputs which is are sensitive to us at any time. 04:10.030 --> 04:14.730 One of the inputs change you'll notice that this process gets evaluated. 04:14.890 --> 04:19.890 And it essentially checks the inputs and puts them to the output. 04:19.990 --> 04:26.440 So you have a begin which is insider process just tells us OK this is where we want to begin in our 04:26.440 --> 04:28.010 process. 04:28.360 --> 04:34.930 We have the case keyword which you notice highlighted in blue we have our win which is just this is 04:34.930 --> 04:36.640 a case statement. 04:36.640 --> 04:43.240 We're taking our case inputs or checking it against any one of these when values which are on lines 04:43.270 --> 04:59.960 29 31 33 35 37 9 1 43 and then the other key word is indicating that if none of the inputs match with 04:59.980 --> 05:07.240 or with any of these when statements this others statement gets evaluated just automatically which in 05:07.240 --> 05:12.930 this case we only have eight different inputs are going to happen so we can cover all of them. 05:12.970 --> 05:20.200 However if we were to have say only we cared about three different inputs then we could just have three 05:20.200 --> 05:21.460 different when statements. 05:21.490 --> 05:24.010 So is a way to catch everything else. 05:24.010 --> 05:27.420 Otherwise all air out because it doesn't know what it. 05:28.040 --> 05:34.850 Now we have in case the word as well as our process in our behavior. 05:35.130 --> 05:39.670 And that is just some syntax for our VHDL file.