Welcome to the if statement case statement lecture in this lecture I'm going to talk about the syntax
and workings of an IF statement as well as a case statement in the VHDL language.
First let's start off by talking about statements.
Their statements are conditional statements that must either evaluate to a true or false condition with
their statements.
We can also have an else statement or clause where the statement does not need to evaluate to TRUE or
FALSE.
If the first condition is not true or does not evaluate to true then we will go ahead and evaluate the
else clause.
Or you can also have an if and if statement.
Meaning if the statement is true or condition is it true you will evaluate the expression nested inside
of your statement.
We'll go through some examples.
A keyword soon if statement are if then else else an end.
And VHDL supports nested if statements so you can have an if statement in a and then another if statement
inside of that and just kind of keep nesting through.
So let's walk through a couple if statement examples.
The first example we have fith enable is equal to 1 then our result is equal to A else.
Our result is equal to others zero.
So if you think no one our conditional statement and table is equal to one.
This is a conditional statement either it's true or false.
If our Nabl is a one to lose all is equal to a far Nabl is zero a result is equal to all the values
are set to zero.
So a couple things we get no result.
A.
They must be the same data type.
Now we know because a result is beings with the keyword in the else clause being the other set to zero.
We know that result and they have to be either standard logic Nectars signed or unsigned data types.
And so this is a valid if statement.
Let's take a look at another example we have.
If enable plus check then result is equal to A and f..
Now this is an if and if statement which is valid.
However our conditional statement does not equal to true or false.
We just have a label plus check that does not equal a 0 or 1 or true or false.
That can be any value.
So this is an invalid if statement for that reason because that conditional statement is not a true
or false.
Now let's take another look if we have an able is equal to a zero then result is equal to A and end
it.
So here we do not have the else clause just the if and if and so this is a valid statement.
What if statements you can do multiple else if we have there is really no limit.
You can do and if else if else if else.
And then an else.
So for example we have if a in the zero the leason if I get that element of that vector is equal to
1 then or encode is equal to zero zero zero.
And if you look through all the else if we have different values if A and one is equal to one then our
own code is 0 0 1 all the way down to LCF or 8 and 7 is equal to a 1 that are code is equal to 1 1 1.
Then we also have the else if none of the.
Or else if statements evaluate to a true then we are going to go and evaluate our statement.
So if our AA and 0 through 7 if none of those are equal to the 1 then our code is going to have the
output of an X or an undefined.
In VHDL language now important thing to note with the LCF statements in VHDL you would think that it
would be spelled like well as e-space.
If however that's not the case it is a class which is slightly confusing but make sure to note that
if you type it you see space I-F it will give you an air and that's an invalid syntax.
So spoke about the case statements in VHDL a case statement checks and inputs against multiple cases.
And the key words for a case statement are case when and and Case No.
When you have a case statement it's important to note the direction of your equals and your arrow sign
as well as your arrow in equals when you're working with Case statements every possible option must
be covered for use the other's keyword.
So conditions cannot overlap.
If I have a case is equal between 1 and 3.
No my next case is equal to a two that becomes invalid because now they overlap.
I have a one in three of my value the two my one in three that I equate to true and my two is in Iowa
true.
So for example we have our case.
We're taking our value inputs and we're saying when our inputs is 0 0 0 the outputs it's going to be
equal to zero zero.
And if we keep following through we have the same type of situation going on we have when our inputs
is equal to 0 0 1 our output is equal to zero one.
And if you notice we cover all different conditions from 0 0 0 to 1 1 1.
We also have the others which is really good to put whenever you have a case statement.
I recommend you always have an other statement.
That way if you forget to cover a certain case that could happen you want to make sure that you give
yourself this kind of an error detection or back false safety function where in this case our outputs
were does give us the Xs or the undefine.
So when you're simulating if you ever see an X or undefined when you're outputs you know that something
is going on with your inputs and you have an air.
If you look at the if statements in the case statements you notice that they're relatively similar.
And if we have a function we can implement or do the same thing in an IF statement Bearse a case statement.
However the key difference is that an IF statement infers priority.
This is because the first statement is true.
It will evaluate that expression and then ignore the rest of the LCS.
However with a case statement we have to cover every possible case and so there is no priority in a
case statement.
You cannot have an overlapping situation where and if else if statement you could have overlapping conditions.
And so with the case statement every single case has the same exact priority.
And so that's just the big difference between a statement or case statement and with an if statement
you do not have to cover every single possibility like you do with the case.
Now you're familiar with F statements and case statements.
Let's start looking at different loops in a VHDL language.