Welcome to the VHDL processes and concurrent statements lecture in this lecture I'm going to talk about
processes and VHDL and concurrent signal assignments.
What is a VHDL process in which a process is a way we set up to determine how do we want to evaluate
certain signals.
That process is evaluated when a signal and a sensitivity list has changed state.
So any signal we put in the sensitivity list of our process if it goes from a high to a low or if we
have a sound logic vector in there any one of those go from a high to a low.
That process is evaluated and Ameche processes contains several parts.
We have to name the sensitivity list the begin statement and the end process statement.
The name is what we use to name our process.
We have multiple processes and a large design the name is just kind of used to help organize and structure
for talking with someone.
You can just define that process and also the sensitivity list is what we use to determine when that
process gets evaluated the begin statement tells us when we want to actually.
Where does our process start.
So we have our process we can instantiate a variable and then we tell it to begin.
And we have our end process statement so take a look at a VHDL process.
We have our name which we're calling state underscore PRC or short from process.
And then we give it the semi-colon and we call it a process and our sensitivity list and the sensitivity
list we have a clock which is a common signal to put in your process.
But what that means is that clock as it's toggling from low to high to high to low.
Every time it makes a transition so it starts out low and goes high.
This process gets evaluated and then as time goes low this process gets evaluated again.
And so then we have our begin statement where we actually start the evaluation process and inside our
process we just have a simple if else statement where if it's the rising edge of our clock then we're
going to check the second IF statement where if a reset is equal to zero then we're setting our state
value to a net else our state value is equal to next state.
And so every time our clock.
Once it's on the rising edge we'll evaluate the if else and if statement if it's the falling edge it's
going to check that if rising edge clock.
And that's not the case so she is going to exit out of that process and you don't have to put a clock
you can put a stat logic vector an integer or any signal inside that process to determine when you want
to evaluate that now it's about the concurrent signal assignments a single assignments are used to assign
a specific value to a signal inside your VHDL design signals can be assigned a set of values such as
a one or a zero or you can have an integer value that you set 1 2 3 4 5 6 so and so forth.
And the big thing you know about signal assignments is that these are concurrent.
So if I have at the very top of my design a equals one and then I have C equals zero a equal get set
to one at the same exact time that C gets set to zero.
These things happen concurrently.
There is no order of.
This happens first this happens second.
It's the same exact time.
So let's take a look at how we do a concurrent signal assignment.
We have our next state is being set to value a state so rapid that we know that next state and state
have to be the same data type.
We cannot assign to different data types one of one data type to one of another.
They have to be the same type.
We have our shift.
We're setting to the value of zero as we all are ADD flow data and data read a data ready are all being
set to the value zero.
Now the important thing to know is at the exact same time that next state is getting the value of state
data ready is getting a value of zero.
So I could rearrange this order and the outputs are going to be the same.
My design is going to act the same.
All these happened simultaneously.
There's no order where one happens and the next one happens so on and so forth.
And that's kind of a huge thing I'm working with FPGA and VHDL.
We had this advantage of parallelism.
I can say I want this to happen at the same exact time this is happening and they will now that we have
finished the VHDL syntax section let's begin looking at the cutting structure.