There is a universal shift register which you know file and I just want it to show you just some of
the uses of the different keywords.
So starting with Line 1 we have a comment just us are just kind of a better thing going on.
And then we've got the library which you notice is highlighted in blue and I Tripoli afterwards is in
red.
We've got the use of Tripoli.
Use Tripoli that gives us allows us to use standard logic vector and Arnstein and sign data types.
And if you look we have entity generic our data with is a type of integer.
RSA is a standard logic vector by on line 11 is a standard logic vector.
This is also standard logic vector and reset clock our standard logic is nimbler that you can see we
have the architecture line 17.
We have a signal which we call a read on line 19 which is the standard logic vector data with why it
minus one down to zero.
So that tells us when we have a data with a we take our with is replace it with 8 8 last one to 7 down
to zero.
So that gives us an a register of 8 bits wide because seven down to zero is a total of eight different
values
and looking below that you can see we've got to begin keyword.
We've got if rising edge is a key word as well which indicates that our clock went a toggle state.
If it's on the rising edge then it evaluates to true if it's on the following edge.
It does not.
And also you look we have a case statement with a win win zero which we're taken our case of x which
is an implied if standard logic vector to down to zero.
So that gives us guys a three
and you can see all the different values that have an ass when it is 0 0.
We hold it Seirawan right shift 1 0.
We left shift and also we have this one others which is an error code which gives us that when others
are a register.
We have to just do this evaluation X which is just like a undetermined value if you have a value of
x that's just saying that you it's more or less just use for your testbench purposes and you looking
to cast Bensons you have a value of x that just means it's undefined or uninitialized or it's an air
value.
Basically that because it can only be a 1 or 0 if even then X it's going to throw an error or make lines
red.
This makes it easier to to catch when you have errors and such is kind of a quick little overview of
how just different keywords and what they look like in the VHDL.