Welcome to the VHDL design structure lecture in this lecture I'm going to explain the structure of HDL
design.
Micheel design elements let's make them include the following elements we have an entity declaration
which this is used to describe the external interfaces to the outside world and the keywords of an entity
declaration or entity is an end.
And we also have an architectural body.
This describes the internal behavior or the operation of our VHDL design.
And the keywords we're using are architectural body is begin and end.
VHDL entities contain both courts and generics.
A port is what specifically used to indicate our inputs and outputs of our design and the generic is
used to more like a replacement or a constant.
So for example we have entity.
Us Are we have a generic and a core are generic.
We're calling data wit and we're setting it to an integer value of eight.
So anywhere where we see the value data wit we can replace that with a value of 8.
And so in your design it makes it easy because this tells us the size of our input and the size of our
output signals a Their output signal and our input signal.
So we plan to change data with in one spot if we want to make it the data within 10.
We just replace it once and our design is now a 10 bit universal shift register.
And for our port.
As I said it's our inputs and outputs.
So we have an architecture which contains signals and everything else.
But what we physically see or what we map is our port values.
Now ports each member has a specific mode and data type.
So the different modes are in which is an input only we have out which is an output only now which is
a bidirectional it can be an input or an output.
And we have a buffer.
And this is an output port that can also be read from inside the architectural body.
Now so for example we you can see we have a data flow to flatter our port which contains that test which
is an output and then the data type which is a standard logic and R C out which we define as an output
with the keyword out the day type of Statter logic and then our X Y and C in our all declaratives inputs
with the keyword in and they're all the same data type of standard logic
generics they do not contain a mode.
They only contain a data type and they're used as a means of passing specific information into the entity.
And neither typically think of them just like a consonant.
So if you have a design and you want to use a value you can pass in as a generic.
You have to change it once and then alter your design you can reference that generic without having
to change multiple lines of code as you come up with more complex and better designs.
The VHDL architecture body This consists of concurrent signal assignment statements process statements
and component instantiation of statements.
This is the whole meaning design.
This is where you're specifying how you want your design to operate.
So you had your entity which tells you design what are my inputs and what are my outputs.
You have the architecture body which says OK I'm taking you then puts in what kind of processing or
what am I doing to the inputs.
And then I specify based on my inputs and internal signals and everything else.
What are my outputs.
So the architecture body is the brains the processing everything that's happening.
We're taking the inputs and we're specifying what we're doing with the outputs.
So if you look we have how do we specify architecture.
Body we have architecture data flow of Flader which flatter one is the same name or entity this or specifying
OK with that entity.
Here is the architecture of that entity.
Now we have the key word is and again this is like the decoration of our architecture body.
Then we have the statement.
This is where we put the concurrent signal assignments the process statements and the component instantiations.
This is where all that goes.
And so in a statement this is where all of the inner workings are taking place we're specifying our
output C out and S given our inputs.
We have to see in X and Y and so given those inputs we're telling it what the outputs are.
Now you're familiar with the structure of VHDL design.
Next we'll look into the different architecture styles.