Welcome to the VHDL design architecture styles lecture in this lecture I'm going to talk to you about
the different styles you can use when you design the architecture of your VHDL design.
So VHDL designs all have to have an entity in architecture in a way design the architecture is you can
use various different ways and three of the common ways are structural behavioral and dataflow structural
design uses component instantiations where we have pre completed HGL designs that we're going to stanchly
in use in our design.
You also have behavioral style which is process statements and we specify the behavior.
Hence the name behavioral.
The behavior of the architecture and we just tell it how we want it to work.
And the compiler determines the number of gates and everything else to make it operate in that way.
And a dataflow style is where we use boolean logic and concurrent signal assignments to the data flow
style we're specifically telling the signals that are coming in which and gates where the OR gates are
and all the different logical gates that are going on of our design.
So we're going to go ahead and walk through all of the different different styles and what we're going
to do is we have a full adder that we're going to go through a behavioral and data flow and the structural
design examples where we're designing the same exact thing we're designing a ladder.
We're just going to use three different architecture styles to do that.
So real quick I'm just going to show you what explain why Flattr is a FULL OUTER has three inputs.
We've got an x y and a Carian.
And you have two outputs carry out and your some.
So what's going on.
We have a truth table but you've got three different inputs and there's no way to assign to these inputs
so the maxim that you could have is a total value of three.
And so it takes whatever the inputs are and gives you the sum on the output.
So if I put my X Y or c in any of those are one and the rest are zeros my output is going to be a 1
on the sum.
And if I put all three are in then I'll have a two on the output and binary gives me a value 3.
So real we're doing is taking Addai as x y and C and and adding them.
So the first example we have let's just talk about a behavioral style architecture.
So a behavioral style architecture does not imply a specific harbor implementation.
We leave this hardware implementation up to the synthesizer that we're using.
And so we simply tell a circuit how we want to behave and the synthesizer will based upon we tell it's
specific timing requirements and it will say OK I think you know it's best served to have an endgame
here and or gate there or whatever it deems the fastest or to meet your requirements by using a behavior
style.
It allows the compiler to determine exactly the the specific implementation.
And I believe behavioral styles are one of the easiest ways to read if you have a fairly complex design.
It is sometimes can be a lot more easy to read.
So let's take an example of the Flader have we're going to use the behavioral data style.
So I'm not going to go through line by line exactly the entire code but it does kind of give you a rough
overview of what's going on and you can kind of see the styles because really important thing here is
to understand the different styles.
So at the beginning we have you know our library we instantiate all of our library using we have the
entity that's telling us our inputs and outputs Terfel that are we have our X Y and C in our ass and
our C out as their outputs.
And then we have the architecture and this is what we're focused on.
So we have the architecture we're calling it behavior and we have our signals inputs and our signal
outputs where we have our signal assignments where we're assigning or inputs the values of c and x Y
and R C out as our outputs one ass as our outputs zero.
Now the key here with the behavioral example.
The big thing we're doing is we have a process we're calling at her proc and in this process we're giving
it a case statement where we're saying our inputs given we have three inputs and for every single case
we're telling you what the outputs should be.
So we're doing a behavior we're saying hey here's our design this how we want it to behave.
Now you go ahead and implement the gates or gates and everything needed to implement this Flader.
But I know that given these inputs I want these outputs and this behavioral style of a flatter the data
flow architecture.
This is what we tell the compiler how to implement the VHDL file by specifically telling it we want
an AND gate here or gate there and you can think of this like we are specifically telling you how we
want the data to flow through our design.
Hence the name dataflow architecture.
So let's take a look at example we have we're going to implement the FLATTR again but this time instead
of a behavioral style We're going to use a dataflow architecture.
So we have the entity.
The libraries are the exact same.
However we have the architecture is the only difference.
So if you'll notice we have after our begin or see out is equal to r c and value added with our X input
exclusive or with our Y input and the result of that is logically ored with the result of the X and
logical ended with the Y input and are some r s value is equal to our X exclusively or with R Y which
is exclusively or with R C in.
And so this is doing the same exact thing as a behavioral style.
This is going to result in the same exact circuitry except in our data flow we're telling exactly which
dates to use that are behavioral synthesizer is determining the gates we're using with a structural
architecture.
This is where you will contain component instantiations of previous designs you've worked on.
This is typically if you have a more complex design or a system where you have a lot of stuff going
on you may have a B and C already completed.
So you pull those designs in and add some of your own custom logic and kind of internally wire them
together.
And we also may include a little bit dataflow style in here.
This is when you're working with complex designs or a lot of times is a very common way of doing things.
So let's take a look at a structural example.
So at a top level we're still doing a full adder and a full outer is created by as is 2 1/2 adder's
So we have a half adder makes the whole design file which you can see we have the half after half an
hour and an OR gate.
And with these 2 1/2 hours in or DAY we're going to create a structural design or FLATTR so with our
structural example we have the library and entity which is the same exact as our data flow and our behavioral
styles.
Now the structural style we have this component instantiation we're instantiating a half after which
contains a Kerry s a and b and we have our internal signals which are half some carry and carry two.
And then what we're doing is we're in stanching or half at or twice.
So we have half hour one and half hour or two and we're assigning these values carry one half some x
y carry to X half some and C in and if you'll notice you look at the carry one and carry two and half
some and how they correlate with the top view block diagram and then we also have a or gate where we're
offering our carry one with our carry two.
And so this is how you implement structural design.
We have this half hour design which is located off somewhere else a separate Be it showed as I M-file.
And we're doing a good point instantiation and it together.
Now you've covered all the different aspects of the design.
Let's start looking at some examples.