Welcome to the test bench introduction lecture and this lecture I'm going to introduce and explain what
a test benches and how that can be used.
A test bench is a model that is used to exercise and verify that your VHDL design is working as you'd
expect.
This is where when you're using these test benches is where most of your debugging will occur.
They're used to verify that the timing and logically that your design is doing as you'd expect when
you're working with me it's G.L..
The challenge is unlike software development you can't emulate or pause your design right in the middle
as it's running and read the value of variables.
You don't have that actual capability.
So with a testbench you can simulate and see what your variables are doing.
And so you can then make the changes accordingly when you're working with a testbench it is most ideal
to have a separate party develop the testbench if at all possible you like for example you want to be
creating the design you want someone else to create the testbench.
That way the testbench has an air or reports in air.
You can then determine either a design is being implemented wrong or B testbench is wrong.
For example if I create a test testbench and I create the design I may create the design wrong and if
I create the test bench wrong making or that's how the design should operate then the test bench is
not of any help to me.
With test benches they consist of an entity and an architecture that entity is empty.
There is no ports or generics.
The architecture it declares that instantiates the design that you want to test and then also the architecture
we're in and generates stimulus that we're in apply to the design we want to test and we'll verify the
response and see what the outputs are.
So just looking at a diagram of what testbench is doing we have our entity to be tested or in this case
the Beechfield design that we create.
And we're going to apply stimulus or simulate in Gennari I want these inputs such as push buttons switches
or other type of inputs you have to your system or design and then you're going to verify the outputs
and see what they are and check if they're correct or also view them on a waveform window to kind of
see how they relate to each other and make sure design is operating as as you expect.
Now when you're working with these test benches these are testing only you cannot synthesize them and
put them on a FPGA.
They are not synthesize they'll give you errors.
There's no actual running designs.
They're simply used only for testing and a test bench can reference from or put in values from outside
files such as text files.
You can use these text files to say create different hex codes you want to apply as an input to your
design and so you can reference these and put them in there but you just have to realize that when you're
writing a testbench for synthesizer will code they are two different and their architectures are different
and they look different and you can actually put a testbench code on the FPGA they're simply for testing
only when you're developing these test benches.
You can code this completely from scratch using any VHDL editor or tool or notepad notepad plus plus
if you're working with Xilinx ISC Xining Silverado or Altera you can get a testbench skeleton to work
from.
So if you click in any one of these three tools you can say I want a testbench file.
It will give you a skeleton so it'll give you the entity and instantiate that device but then you still
have to tell it or generate the stimulus for this testbench.
Now you know in test benches.
Let's take a look at the structure of a VHDL testbench.