Here's a walkthrough of just kind of example outline of what a test bench would look like.
Now this actual This code here wouldn't actually work.
It's just kind of a skeleton or like what a test bench would look like.
So if you look at line 1 we've got comments and then lines three through five are where we call in the
libraries as well as standard logic 1 1 6 4.
Also the numeric standard model all which allows us to use the center vector center logic vectors and
the signed and unsigned types.
Now libraries that are only supporter in test benches you can see here we have as the standard text
I know and standard logic text.
And this allows us to actually read in values from a text file.
We have the entity which we just whatever name we call the testbench which normally we call it test
underscore whatever the name of the actual design you're testing.
And then we have the architecture test and this is where we instantiate the component of the VHDL entity
we're testing.
And we have the component names we essentially do the component instantiation and then in the to do
section right on line 25 we want to create signals that we're going to use in our testbench.
And then after that in the begin we want to call some of them to test but we'll create the name of entity
to.
We're testing port map and everything there.
And then we'll have our expected process.
Mine 33 and this is just a process where we're going to specify.
It's going to give us the results we want.
So the testbench is essentially we're generating inputs and this is a stimulus process 140 or C that
is where we're actually generating inputs to put on the shelf while we are we're testing and then we
want to check the outputs unexpected process and the end if we get if the results are not what we expect
then we know that our design is not working correctly.
And so that's just kind of how novio But what a test bench looks like and kind of what when we create
one this is kind of what the code will look like.