Welcome the module 7.1 model asem model some model Semb is an extremely powerful tool set that is used
to simulate and test your VHDL designs all the labs include Moulson screenshot showing you what the
output of your design should look like.
You can code your VHDL design inside a model.
However I prefer to use notepad plus plus which is a free tool that allows you to edit VHDL files simulation
steps.
Here is a list of all the simulation steps to create project and models.
I would suggest to use this as a reference to simulate the VHDL designs in the labs.
Step one is to create all necessary VHDL files.
Step two is to navigate to your VHDL design directory.
Step three is to create a model SCM library.
Step 4 is to compile and simulate your design.
The first step is to create all the necessary files which includes one the design file.
This is the file that contains your VHDL design to the test bench file which I will be providing for
you.
3.
The TCM script I will be providing this for you as well.
When organizing your VHDL designs I suggest organizing them as shown in the image on the right opening
model.
Now fire up model sim and your screen should look something like this.
Step Two change directory.
Step 2 is to click on File change directory and then navigate to the folder where your VHDL code is
located.
Note that you will have to do this every time you open Moulson.
Step 3 create a library.
The next step is to create a model some library.
Every time you navigate to a new directory you will have to create a model some library in order to
create a massive library click on File new new library the default library name for Moulson is work.
Make sure that a new library and logical mapping to it is selected step for compile the next step is
to compile the VHDL design in order to do that.
You need to quit compile compile and then select your VHDL design and test files.
Any errors located in your VHDL design will show up in the transcript window.
Step Five simulate the next step is to simulate your design in order to do this you must expand the
work library and the library window.
Then double click on the test bench VHDL entity.
This will launch the model sim simulation window.
In this sim default window right click on the dev two test or Yuichi instance and navigate to add to
waive all items in region.
The final step is to type run in however long you want your design to run for Step Five simulate.
Here's a screenshot showing how to add all items to the simulation window.
Step 4 and 5 you can combine steps 4 and 5 into one easy step with the use of a DCL script HECS script
stands for tool command line which is a set of instructions that tell us what to do.
I will provide you with all the TC scripts needed to complete the labs step 4 and 5.
Here is a screenshot showing you how to navigate to run a TCO file.
Tips and Tricks.
Here's a little tip to use after your simulation has completed.
Right click on the simulation window and select zoom full.
This will evilest base the signals so you can see the entire simulation.
Tips and Tricks here are a few tips and tricks that I feel make reading the simulation easier.
If you have any other questions click on the help and then select the PTF documentation and there is
a list of help documents at your disposal.
Also there are many forums online that if you search you can find a lot of the information you are looking
for.
If you're having troubles you cannot figure out.
Feel free to send me an email and I will do my best to help you.
We have just finished Marjoe 7.1 Moulson.
Here's a summary of some of the things we went over.
You need to have a model library for every project.
You cannot manually compile he or you can manually compile and simulate your designs.
However using a typical scripts are a much easier and faster way of simulating.