library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;


entity lcd is
    Port ( clk,start : in STD_LOGIC;
           rs,en,rw : out STD_LOGIC;
           dout : out STD_LOGIC_VECTOR (7 downto 0));
end lcd;

architecture Behavioral of lcd is
-------------------2D Array for LCD Command and Data ------------------------
type lcd_data is array (7 downto 0) of std_logic_vector(7 downto 0);
constant data : lcd_data := (X"38", X"0C", X"06", X"01", X"C0", X"41", X"42",X"43");
--------------Registering Status of EN, RW and RS ---------------------------
signal ent,rst,rwt : std_logic := '0';

-----------------------Counter Variable ----------------------
signal count : integer range 0 to 5 := 0;  ----Slower Clock Counter
signal dcount : integer range 0 to 10 := 0;  ----- Counter for tracking lcd data 
-----------------------State Machine ----------------------------------
type state_type is (idle, command);
signal state: state_type;

begin
slower_process:process(clk)
begin
if(count < 5) then
   count <= count + 1;
else
   count <= 0;
   ent <= not ent;
end if;
end process;

data_process:process(ent)
begin
if(rising_edge(ent)) then
case(state) is
when idle =>
    if(start = '1') then
        state <= command;
     else
        state <= idle;
    end if;

when command =>
   if (dcount < 5) then
      rst <= '0';
      rwt <= '0';
      dcount <= dcount + 1;
      dout <= data(7- dcount);
   elsif (5 <=  dcount  and dcount < 8) then
      rwt <= '0';
      rst <= '1';    
      dcount <= dcount + 1;
      dout <= data(7 - dcount);
   else
       dcount <= 0;
       state <= idle;
       rwt <= '1';
   end if;
when others =>
       state <= idle;
 end case;
 end if;
end process;

en <= ent;
rw <= rwt;
rs <= rst;

end Behavioral;